A programmable clock generator HDL softcore

被引：3

作者：

Eisenreich, H. ^{[1
]}

Mayr, C. ^{[1
]}

Henker, S. ^{[1
]}

Wickert, M. ^{[1
]}

Schueffny, R. ^{[1
]}

机构：

[1] Tech Univ Dresden, Circuits & Syst Lab, D-8027 Dresden, Germany

来源：

2007 50TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3 | 2007年

关键词：

D O I：

10.1109/MWSCAS.2007.4488528

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a hardware implementation of a fully synthesizable, technology independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter. Frequency control is done by using a robust regulation algorithm to allow a defined lock in time of at most 8 reference cycles. ASICs in CMOS AMS 0,35um and UMC 0,13um have been manufactured and tested. Measurements show competitive results to state-of-theart mixed signal implementations.

引用

页码：1 / 4

页数：4

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