Accelerating Decision Tree Based Traffic Classification on FPGA and Multicore Platforms

被引:61
作者
Tong, Da [1 ]
Qu, Yun Rock [2 ]
Prasanna, Viktor K. [3 ]
机构
[1] VMware Inc, 3401 Hillview Ave, Palo Alto, CA 94304 USA
[2] Xilinx Inc, 2100 Logic Dr, San Jose, CA 95124 USA
[3] Univ Southern Calif, Dept Elect Engn, Los Angeles, CA 90089 USA
基金
美国国家科学基金会;
关键词
Traffic classification; machine learning; decision tree; multicore; FPGA; high throughput; SUPPORT VECTOR MACHINES;
D O I
10.1109/TPDS.2017.2714661
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Machine learning (ML) algorithms have been shown to be effective in classifying a broad range of applications in the Internet traffic. In this paper, we propose algorithms and architectures to realize online traffic classification using flow level features. First, we develop a traffic classifier based on C4.5 decision tree algorithm and Entropy-MDL (Minimum Description Length) discretization algorithm. It achieves an overall accuracy of 97.92 percent for classifying eight major applications. Next we propose approaches to accelerate the classifier on FPGA (Field Programmable Gate Array) and multicore platforms. We optimize the original classifier by merging it with discretization. Our implementation of this optimized decision tree achieves 7500+Million Classifications Per Second (MCPS) on a state-of-the-art FPGA platform and 75-150 MCPS on two state-of-the-art multicore platforms. We also propose a divide and conquer approach to handle imbalanced decision trees. Our implementation of the divide-and-conquer approach achieves 10,000+MCPS on a state-of-the-art FPGA platform and 130-340 MCPS on two state-of-the-art multicore platforms. We conduct extensive experiments on both platforms for various application scenarios to compare the two approaches.
引用
收藏
页码:3046 / 3059
页数:14
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