A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer

被引：31

作者：

Chen, Wei-Zen ^{[1
]}

Huang, Shih-Hao ^{[1
]}

Wu, Guo-Wei ^{[1
]}

Liu, Chuan-Chang ^{[1
]}

Huang, Yang-Tung ^{[1
]}

Chiu, Chin-Fong ^{[2
]}

Chang, Wen-Hsu ^{[2
]}

Juang, Ying-Zong ^{[2
]}

机构：

[1] Natl Chiao Tung Univ, Dept Elect Engn, 1001 Ta Hsueh Rd, Hsinchu, Taiwan

[2] Natl Chip Implementat Ctr, Natl Appl Res Labs, Hsinchu 300, Taiwan

来源：

2007 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS | 2007年

关键词：

D O I：

10.1109/ASSCC.2007.4425714

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the design of a 3.125 Gbps monolithic CMOS optical receiver, integrating a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. The optical receiver is capable of delivering 420 mV(PP) to 50 Omega output load after optical to electrical conversion. High speed operation is achieved by utilizing spatial modulated light (SML) detector and adaptive analog equalizer. Implemented in a 0.18 mu m CMOS technology, the total power dissipation is 175 mW. The chip size is 0.7 mm(2).

引用

页码：396 / +

页数：2

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