Exploring the Influence of Variability on Single-Electron Transistors Into SET-Based Circuits

被引：17

作者：

Amat, Esteve ^{[1
]}

Bausells, Joan ^{[1
]}

Perez-Murano, Francesc ^{[1
]}

机构：

[1] Barcelona Microelect Inst, Natl Microelect Ctr, Barcelona 08193, Spain

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2017年 / 64卷 / 12期

关键词：

MOSFET; single-electron transistor (SET); variability; COMPACT ANALYTICAL-MODEL; DEVICES;

D O I：

10.1109/TED.2017.2765003

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We analyze the performance of hybrid single-electron transistor (SET)-FET circuits when different variability sources are considered, e.g., SET's quantum dot location and FET device dimension variations. For the FET device, FinFET and vertical nanowire configurations have been studied. The hybrid SET-FET circuits with both SET and FET in vertical topology depict the best circuit performance and the highest integration level. The variability impact on different SET-based circuits has been analyzed, including negative differential resistance and logic inverters.

引用

页码：5172 / 5180

页数：9

共 25 条

[1]

Amat E., 2017, P SPAN C EL DEV FEB, P1

[2] Vertical single electron transistors with separate gates [J].

Austing, DG ;

Honda, T ;

Tarucha, S .

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 1997, 36 (6B) :4151-4155

[3] Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession [J].

Chiarella, T. ;

Witters, L. ;

Mercha, A. ;

Kerner, C. ;

Rakowski, M. ;

Ortolland, C. ;

Ragnarsson, L. -A. ;

Parvais, B. ;

De Keersgieter, A. ;

Kubicek, S. ;

Redolfi, A. ;

Vrancken, C. ;

Brus, S. ;

Lauwers, A. ;

Absil, P. ;

Biesemans, S. ;

Hoffmann, T. .

SOLID-STATE ELECTRONICS, 2010, 54 (09) :855-860

[4]

Deshpande V., 2012, IEDM

[5] A hybrid CMOS-SET co-fabrication platform using nano-grain polysilicon wires [J].

Ecoffey, S ;

Pott, V ;

Mahapatra, S ;

Bouvet, D ;

Fazan, P ;

Ionescu, AM .

MICROELECTRONIC ENGINEERING, 2005, 78-79 :239-243

[6] A compact analytical model for asymmetric single-electron tunneling transistors [J].

Inokawa, H ;

Takahashi, Y .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (02) :455-461

[7] Mass Production of Silicon MOS-SETs: Can We Live with Nano-Devices' Variability? [J].

Jehl, X. ;

Roche, B. ;

Sanquer, M. ;

Voisin, B. ;

Wacquez, R. ;

Deshpande, V. ;

Previtali, B. ;

Vinet, M. ;

Verduijn, J. ;

Tettamanzi, G. C. ;

Rogge, S. ;

Kotekar-Patil, D. ;

Ruoff, M. ;

Kern, D. ;

Wharam, D. A. ;

Belli, M. ;

Prati, E. ;

Fanciulli, M. .

PROCEEDINGS OF THE 2ND EUROPEAN FUTURE TECHNOLOGIES CONFERENCE AND EXHIBITION 2011 (FET 11), 2011, 7 :266-268

[8]

Klüpfel FJ, 2016, INT CONF SIM SEMI PR, P237, DOI 10.1109/SISPAD.2016.7605191

[9] Simulating hybrid circuits of single-electron transistors and field-effect transistors [J].

Lientschnig, G ;

Weymann, I ;

Hadley, P .

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2003, 42 (10) :6467-6472

[10] Single-electron devices and their applications [J].

Likharev, KK .

PROCEEDINGS OF THE IEEE, 1999, 87 (04) :606-632

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