Harmonic Analysis of Common-mode Reduction Modulation for Three-level Inverter

被引：0

作者：

Chen, Ruirui ^{[1
]}

Niu, Jiahao ^{[1
]}

Gui, Handong ^{[1
]}

Zhang, Zheyu ^{[4
]}

Wang, Fred ^{[1
,2
]}

Tolbert, Leon M. ^{[1
,2
]}

Blalock, Benjamin J. ^{[1
]}

Costinett, Daniel J. ^{[1
,2
]}

Choi, Benjamin B. ^{[3
]}

机构：

[1] Univ Tennessee, Min H Kao Dept Elect Engn & Comp Sci, Knoxville, TN 37996 USA

[2] Oak Ridge Natl Lab, Knoxville, TN USA

[3] NASA, Glenn Res Ctr, Cleveland, OH USA

[4] Clemson Univ, Restorat Inst, Clemson, SC 29631 USA

来源：

2019 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE) | 2019年

基金：

美国国家科学基金会;

关键词：

Three-level converter; common-mode voltage; SVM; harmonics; EMI noise; VOLTAGE REDUCTION; PWM TECHNIQUE;

D O I：

10.1109/ecce.2019.8912187

中图分类号：

TE [石油、天然气工业]; TK [能源与动力工程];

学科分类号：

0807 ; 0820 ;

摘要：

This paper presents harmonic analysis of common-mode reduction (CMR) modulation for three-level voltage source inverters. The analytical model to calculate the harmonics of CMR modulation with arbitrary PWM sequence is developed. The impact of alternative PWM sequences of CMR modulation on harmonics is investigated. New three-state and four-state PWM sequences of CMR are proposed which spread the energy centered in the carrier frequency in the conventional CMR, and thus reduce the voltage peaks in frequency domain. Experiments are conducted on a three-level neutral point clamped inverter. Experiment results verify the developed analytical model and harmonic analysis.

引用

页码：2286 / 2293

页数：8

共 13 条

[1] Reduction of common-mode currents in PWM inverter motor drives [J].

Cacciato, M ;

Consoli, A ;

Scarcella, G ;

Testa, A .

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, 1999, 35 (02) :469-476

[2]

Chen RR, 2019, APPL POWER ELECT CO, P112, DOI 10.1109/APEC.2019.8721981

[3] Contour-Based Dead-Time Harmonic Analysis in a Three-Level Neutral-Point-Clamped Inverter [J].

Dolguntseva, Irina ;

Krishna, Remya ;

Soman, Deepak E. ;

Leijon, Mats .

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2015, 62 (01) :203-210

[4] Performance Analysis of Reduced Common-Mode Voltage PWM Methods and Comparison With Standard PWM Methods for Three-Phase Voltage-Source Inverters [J].

Hava, Ahmet M. ;

Un, Emre .

IEEE TRANSACTIONS ON POWER ELECTRONICS, 2009, 24 (1-2) :241-252

[5]

Holmes D.Grahame., 2003, PULSE WIDTH MODULATI

[6] A new PWM strategy for common-mode voltage reduction in neutral-point-clamped inverter-fed AC motor drives [J].

Kim, HJ ;

Lee, HD ;

Sul, SK .

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, 2001, 37 (06) :1840-1845

[7] Optimal common-mode voltage reduction PWM technique for inverter control with consideration of the dead-time effects - Part II: Applications to IM drives with diode front end [J].

Lai, YS ;

Chen, PS ;

Lee, HK ;

Chou, J .

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, 2004, 40 (06) :1613-1620

[8]

Lai YS, 2004, IEEE T IND APPL, V40, P1605, DOI 10.1109/TIA.2004.836149

[9] A General Analytical Method for Calculating Inverter DC-Link Current Harmonics [J].

McGrath, Brendan Peter ;

Holmes, Donald Grahame .

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, 2009, 45 (05) :1851-1859

[10]

Pratibha N, 2016, PROCEEDINGS OF THE 2016 IEEE REGION 10 CONFERENCE (TENCON), P697, DOI 10.1109/TENCON.2016.7848092

← 1 2 →