A 1.2 V Single Supply Hybrid Current-/Voltage-Mode Three-Way Digital Doherty PA with Built-In Large-Signal Phase Compensation Achieving Less-Than 5° AM-PM

被引：0

作者：

Jung, Doohwan ^{[1
]}

Park, Jongseok ^{[1
]}

Li, Sensen ^{[1
]}

Huang, Tzu-Yuan ^{[1
]}

Zhao, Huan ^{[2
]}

Wang, Hua ^{[1
]}

机构：

[1] Georgia Tech, Sch Elect & Comp Engn, Atlanta, GA 30332 USA

[2] Kangxi Commun Technol Shanghai Co Ltd, Sanghai, Peoples R China

来源：

2019 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) | 2019年

关键词：

AM-PM compensation; CMOS integrated circuits; digital Doherty power amplifier (PA); linearity; polar modulation; POWER-AMPLIFIER;

D O I：

10.1109/CICC.2019.8780290

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a single supply (1.2V) hybrid current-/voltage-mode three-way digital Doherty PA with built-in large-signal phase compensation technique to improve the power amplifier (PA) efficiency at deep power back-off (PBO), substantially reduce AM-PM distortion, and further simply supply power management. The design leverages one currentmode digital PA (C-DPA) as the main path and two voltage-mode digital PAs (4-DPAs) as the two auxiliary paths, combined by three-way transformer-based series Doherty output network. As a proof-of-concept. the three-way hybrid digital Doherty PA is implemented in 45 urn CMOS SOI process occupying 3 mm-by-2 mm. It achieves +22.4 dam peak output power (Put) together with 38.5/32.1/18.7% drain efficiency (DE) for the peak/3.419.3 dB output power back-off (PBO) at 2.3 Gila, The proposed digital Doherty PA demonstrates 1.268/1.468 PBO efficiency enhancement, compared to an ideal class-B implementation at 3.4/9.3 dB PBO. The maximum AM-PM distortion is 4.7 at 2.3 GHz without using AM-PM look-up table (LIT). The measured error sector magnitude (EVM) of 64-QAM/40 MHz and 256QAM/10 MHz are-32 dB and -32,1 dB with 24.7% and 23,2% average DE without AM-PM LUT.

引用

页数：4