A 0.314μm2 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography

被引：29

作者：

Nackaerts, A ^{[1
]}

Ercken, M ^{[1
]}

Demuynck, S ^{[1
]}

Lauwers, A ^{[1
]}

Baerts, C ^{[1
]}

Bender, H ^{[1
]}

Boulaert, W ^{[1
]}

Collaert, N ^{[1
]}

Degroote, B ^{[1
]}

Delvaux, C ^{[1
]}

de Marneffe, JF ^{[1
]}

Dixit, A ^{[1
]}

De Meyer, K ^{[1
]}

Hendrickx, E ^{[1
]}

Heylen, N ^{[1
]}

Jaenen, P ^{[1
]}

Laidler, D ^{[1
]}

Locorotondo, S ^{[1
]}

Maenhoudt, M ^{[1
]}

Moelants, M ^{[1
]}

Pollentier, I ^{[1
]}

Ronse, K ^{[1
]}

Rooyackers, R ^{[1
]}

Van Aelst, J ^{[1
]}

Vandenberghe, G ^{[1
]}

Vandervorst, W ^{[1
]}

Vandeweyer, T ^{[1
]}

Vanhaelemeersch, S ^{[1
]}

Van Hove, M ^{[1
]}

Van Olmen, J ^{[1
]}

Verhaegen, S ^{[1
]}

Versluijs, J ^{[1
]}

Vrancken, C ^{[1
]}

Wiaux, V ^{[1
]}

Jurczak, M ^{[1
]}

Bisemans, S ^{[1
]}

机构：

[1] IMEC, B-3001 Heverlee, Belgium

来源：

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST | 2004年

关键词：

D O I：

10.1109/IEDM.2004.1419129

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes the fabrication process of a fully working 6T-SRAM cell of 0.314mum2 build with Tall Triple Gate (TTG) devices. A high static noise margin of 172 mV is obtained at 0.6 V operation. Transistors with 40nm physical gate length, 70nm tall & 35nm wide fins, 35nm wide HDD spacer are used. Low-tilt extension/HALO implants, NiSi and Cu/Low-K BEOL are some of the key features. This is an experimental demonstration of a fully working Tall Triple Gate SRAM cell with the smallest cell size ever reported.

引用

页码：269 / 272

页数：4