A 14-bit 100-msample/s subranging ADC

被引：20

作者：

Moreland, C ^{[1
]}

Murden, F ^{[1
]}

Elliott, M ^{[1
]}

Young, J ^{[1
]}

Hensley, M ^{[1
]}

Stop, R ^{[1
]}

机构：

[1] Analog Devices Inc, Greensboro, NC 27409 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2000年 / 35卷 / 12期

关键词：

ADC; analog-to-digital; complementary bipolar; converter; folding amplifier; sample-and-hold; SOI; subranging;

D O I：

10.1109/4.890292

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a 14-b analog-to-digital converter designed in a complementary bipolar process. Although it uses a fairly traditional three-stage subranging architecture, several nontraditional techniques are incorporated to achieve 14 bits of performance at a clerk rate of 100 MHz, For linearity, the most critical of these is wafer-level trimming of the first subrange digital-to-analog converter. Prototype silicon exhibits a spurious-free dynamic range of 90 dB through the Nyquist frequency and a signal-to-noise ratio of 74 dB while dissipating 1.25 W.

引用

页码：1791 / 1798

页数：8