A 10b 42MS/s SAR ADC with Power Efficient Design

被引：2

作者：

Hu Hongfei ^{[1
]}

Liu Yihua ^{[1
]}

Li Xiaopeng ^{[2
]}

Zhang Youtao ^{[2
]}

Guo Yufeng ^{[1
]}

Gao Hao ^{[3
,4
]}

Zhang Yi ^{[1
]}

机构：

[1] Nanjing Univ Posts & Telecommun, Nanjing, Peoples R China

[2] Nanjing GuoBo Elect Co Ltd, Nanjing, Peoples R China

[3] Silicon Austria Labs, Linz, Austria

[4] Eindhoven Univ Technol, Eindhoven, Netherlands

来源：

2021 THE 6TH INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS AND MICROSYSTEMS (ICICM 2021) | 2021年

基金：

中国博士后科学基金; 中国国家自然科学基金;

关键词：

Analog-to-digital converter (ADC); energy efficient; successive approximation register (SAR); 10-BIT;

D O I：

10.1109/ICICM54364.2021.9660351

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 10b 42MS/s power-efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) is presented in this paper. The ADC structure is optimized for lower power consumption. For this purpose, an accuracy-enhanced DAC switching method and a comparator that can dynamically adjust current to save energy are introduced. The linearity of SAR ADCs can be improved without adding capacitors or calibration logic in this way. In 130nm CMOS process, simulation results show the ADC achieves a SNDR of 60dB for Nyquist input and consumes 510 mu W under a 1.2V power supply.

引用

页码：1 / 4

页数：4

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