Reliability of Fan-Out Wafer Level Packaging For III-V RF Power MMICs

This paper describes an approach for the evaluation of reliability of a heterogeneous integration of gallium nitride (GaN) and gallium arsenide (GaAs) RF power monolithic microwave integrated circuits (MMICs) in a Fan-Out Wafer-Level Packaging (FOWLP) configuration. The methodological approach presented here combines accelerated ageing tests and physical simulations to assess the package reliability. Multiple challenges are encountered in the integration and reliability of GaN and GaAs chips in FOWLP. The limiting factors in the GaN integration are the thermal dissipation due to the high power and the thermomechanical behavior of the package. To apprehend such behaviors, test structures have been especially designed. A structure is dedicated to the evaluation of the package thermal resistance (Rth). The output characteristic comes from a transistor in a common source configuration, with the drain shorted and the gate voltage close to zero to allow almost no current in the transistor. Rth values are calculated via measurements of the gate resistance and the use of abacus of equivalence. Moreover, thermo-mechanical stress sensors (based on GaN active zone) are manufactured to evaluate the deformation during assembly and operating life. The sensors can be assimilated to active resistances along the four edges of the die. They have been measured on wafer to serve as reference. By measuring them, the sheet resistance can be extracted and the thermal coefficients calculated. Both structures are encapsulated in FOWLP. To complete the study, thermomechanical simulations will be made. It will permit to numerically evaluate the limits of the System in Package (SiP) when modelled with the in-situ viscoelaslic properties of materials of the package.