Ultra Low Power Full Adder Circuit using Carbon Nanotube Field Effect Transistor

被引:0
作者
Kumar, Koushik [1 ]
Sahithi, Chittineni [1 ]
Sahoo, Rasmita [1 ]
Sahoo, Subhendu Kumar [1 ]
机构
[1] BITS Pilani, Dept Elect & Elect Engn, Hyderabad Campus, Hyderabad, Andhra Pradesh, India
来源
2014 INTERNATIONAL CONFERENCE ON POWER, CONTROL AND EMBEDDED SYSTEMS (ICPCES) | 2014年
关键词
CNTFET; Low power; Adder; CMOS;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
After the invention of the MOSFET, continuous scaling of the device is going on as predicted by Moore in 1970. This reduction in device size is giving higher performance in terms of increased speed, lower power consumption at lower cost with greater chip density. At the same time, because of the scaling, the channel length is decreasing continuously leading to short-channel effects (SCE) in nanoscale regime. To overcome these limitations many alternate devices are proposed. Among these various alternative devices, carbon nanotube field effect transistor (CNTFET) is found to be one of the most promising alternatives for MOSFET. The CNTFET is a field effect transistor in which a carbon nanotube (CNT) is used in the channel region. In this paper we have used CNTFETs for designing a 10 transistor adder circuit, from which power, delay and power delay products are calculated. We have then calculated all these performance parameters for CMOS logic and compared the results with that obtained for CNTFET logic. The comparison shows circuits using CNTFET consumes almost 80 percent less power compared to its CMOS counterpart and hence advantageous over CMOS design.
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页数:3
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