Impact of Interface Trap Charges on Analog/RF and Linearity Performances of Dual-Material Gate-Oxide-Stack Double-Gate TFET

被引：72
作者：
Singh, Km. Sucheta [1 ]
Kumar, Satyendra [1 ]
Nigam, Kaushal [1 ]
机构：
[1] Jaypee Inst Informat Technol, Dept ECE, Noida 201304, India
来源：
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY | 2020年 / 20卷 / 02期
关键词：
Work-function engineering; tunnel field effect transistor; interface trap charges; gate-oxide stack; DOPED TUNNEL FET; MOSFET; TRANSISTOR; DESIGN; MODEL;
D O I：
10.1109/TDMR.2020.2984669
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper investigates the impact of different interface trap charges (ITCs) on dual-material gate-oxide-stack double-gate TFET (DMGOSDG-TFET) by introducing localized charges (donor/acceptor) at the interface of semiconductor/insulator. For this, we have observed the effects of different ITCs on both conventional dual material control gate tunnel field effect transistor (DMCG-TFET) and dual-material gate-oxide-stack double-gate TFET with identical dimensions in terms of DC, analog/RF and linearity performance parameters. Both the devices with positive (donor) and negative (acceptor) ITCs, have been simulated using technology computer-aided design (TCAD) tool. To understand the impact of different ITCs on the DC and analog/RF performances, the parameters such as electric field, transfer characteristics, transconductance, parasitic capacitance, f(T), GBP and TFP for DMGOSDG-TFET have been analyzed and compared with that of DMCG-TFET. Further, to analyze the effect of different ITCs on the linearity performances, the parameters VIP2, VIP3, IIP3 and IMD3 have been investigated and compared with that of the conventional DMCG-TFET. Simulation results demonstrate that DMGOSDG-TFET is more immune towards different types of ITCs as compared to the conventional DMCG-TFET. Hence, DMGOSDG-TFET is more reliable over the conventional device for ultra low power applications.
引用
收藏
页码：404 / 412
页数：9
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