Optimum Circuits for Bit Reversal

被引：36

作者：

Garrido, Mario ^{[1
]}

Grajal, Jesus ^{[2
]}

Gustafsson, Oscar ^{[1
]}

机构：

[1] Linkoping Univ, Dept Elect Engn, S-58183 Linkoping, Sweden

[2] Univ Politecn Madrid, Dept Signal Syst & Radiocommun, E-28040 Madrid, Spain

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2011年 / 58卷 / 10期

关键词：

Bit reversal; fast Fourier transform (FFT); pipelined architecture; FFT; PERMUTATION;

D O I：

10.1109/TCSII.2011.2164141

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This brief presents novel circuits for calculating bit reversal on a series of data. The circuits are simple and consist of buffers and multiplexers connected in series. The circuits are optimum in two senses: they use the minimum number of registers that are necessary for calculating the bit reversal and have minimum latency. This makes them very suitable for calculating the bit reversal of the output frequencies in hardware fast Fourier transform (FFT) architectures. This brief also proposes optimum solutions for reordering the output frequencies of the FFT when different common radices are used, including radix-2, radix-2(k), radix-4, and radix-8.

引用

页码：657 / 661

页数：5

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