A Two-Stage ADC Architecture With VCO-Based Second Stage

被引：25

作者：

Gupta, A. K. ^{[1
,2
]}

Nagaraj, K. ^{[2
]}

Viswanathan, T. R. ^{[1
]}

机构：

[1] Univ Texas Austin, Dept Elect & Comp Engn, Austin, TX 78712 USA

[2] Texas Instruments Inc, Dallas, TX 75243 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2011年 / 58卷 / 11期

关键词：

Analog-to-digital converter (ADC); calibration; time-to-digital converter (TDC); two-step ADC; voltage-controlled oscillators (VCOs);

D O I：

10.1109/TCSII.2011.2168015

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This brief describes the design of a two-stage analog-to-digital converter (ADC) with voltage-controlled oscillator (VCO)-based second stage. The advantages of quantizing the first-stage residue in time domain versus traditional voltage domain are presented. The dc gain requirement of the first-stage residue amplifier is relaxed by reference-scaling and reference-recycling schemes. This enables the use of a very simple telescopic cascode amplifier in the gain stage. The second-stage VCO linearity is improved by a differential measurement of VCO frequency. Power consumption in the second stage is reduced by time-to-digital conversion for fine quantization of the VCO phase. Simulation results are presented for the design of a 13-bit 20-Msps ADC in 65-nm CMOS process. The estimated power dissipation of this converter is less than 1 mW.

引用

页码：734 / 738

页数：5

共 18 条

[1] A 10-bit pipeline ADC using 40-dB opamps and calibrated customized references [J].

Chen, Cheng ;

Yuan, Jiren .

ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, :249-252

[2] A highly linear CMOS current-controlled oscillator using a novel frequency detector [J].

Cui, Su ;

Viswanathan, T. Lakshmi ;

Viswanathan, T. R. ;

Banerjee, Bhaskar .

PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, :2841-+

[3] A 10mW 9.7ENOB 80MSPS Pipeline ADC in 65nm CMOS Process without any Special Mask Requirement and with single 1.3V supply [J].

Das, Abhijit Kumar ;

Bhasin, Hemant ;

Giduturi, Sundara Siva Rao .

PROCEEDINGS OF THE IEEE 2009 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2009, :165-168

[4] Background interstage gain calibration technique for pipelined ADCs [J].

Keane, JP ;

Hurst, PJ ;

Lewis, SH .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2005, 52 (01) :32-43

[5] Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter [J].

Kim, Jaewook ;

Jang, Tae-Kwang ;

Yoon, Young-Gyu ;

Cho, SeongHwan .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2010, 57 (01) :18-30

[6] A 12b 50MS/s 3.5mW SAR Assisted 2-Stage Pipeline ADC [J].

Lee, Chun C. ;

Flynn, Michael P. .

2010 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2010, :239-240

[7] A 65nm CMOS 1.2V 12b 30MS/s ADC with Capacitive Reference Scaling [J].

Lee, Kang-Jin ;

Moon, Kyoung-Jun ;

Ma, Kwang-Sung ;

Moon, Kyoung-Ho ;

Kim, Jae-Whui .

PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2008, :165-168

[8] OPTIMIZING THE STAGE RESOLUTION IN PIPELINED, MULTISTAGE, ANALOG-TO-DIGITAL CONVERTERS FOR VIDEO-RATE APPLICATIONS [J].

LEWIS, SH .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1992, 39 (08) :516-523

[9] Delay-Line-Based Analog-to-Digital Converters [J].

Li, Guansheng ;

Tousi, Yahya M. ;

Hassibi, Arjang ;

Afshari, Ehsan .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2009, 56 (06) :464-468

[10] Noise-shaped integrating quantisers in ΔΣ modulators [J].

Maghari, N. ;

Temes, G. C. ;

Moon, U. .

ELECTRONICS LETTERS, 2009, 45 (12) :612-U11

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