On the Reliability of Interconnected CMOS Gates Considering MOSFET Threshold-Voltage Variations

被引：0

作者：

Sulieman, Mawahib Hussein ^{[1
]}

机构：

[1] UAE Univ, Dept Elect Engn, Al Ain, U Arab Emirates

来源：

NANO-NET | 2009年 / 20卷

关键词：

Reliability; threshold voltage; CMOS; gates;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper discusses the effects of MOSFET threshold voltage variations on the reliability of nanometer-scale CMOS logic gates. The reliability is quantified in terms of the probability-of-failure of individual CMOS gates, which is obtained from extensive Monte Carlo simulations of these gates. The study considers different nano-scale CMOS technology generations and compares the effect of threshold voltage variations on the reliability at the gate level. The results presented here show a clear dependency pattern of reliability on the gate's input combinations (vectors). The results also show that both the NAND and Majority logic gates can tolerate up to 40% of threshold voltage variations in a 90nm technology, while only up to 20% at the 22nm technology node.

引用

页码：251 / 258

页数：8

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