On the Reliability of Interconnected CMOS Gates Considering MOSFET Threshold-Voltage Variations

This paper discusses the effects of MOSFET threshold voltage variations on the reliability of nanometer-scale CMOS logic gates. The reliability is quantified in terms of the probability-of-failure of individual CMOS gates, which is obtained from extensive Monte Carlo simulations of these gates. The study considers different nano-scale CMOS technology generations and compares the effect of threshold voltage variations on the reliability at the gate level. The results presented here show a clear dependency pattern of reliability on the gate's input combinations (vectors). The results also show that both the NAND and Majority logic gates can tolerate up to 40% of threshold voltage variations in a 90nm technology, while only up to 20% at the 22nm technology node.