Fine-grained sleep transistor sizing algorithm for leakage power minimization

被引：17

作者：

Chiou, De-Shiuan ^{[1
]}

Juan, Da-Cheng ^{[1
]}

Chen, Yu-Ting ^{[1
]}

Chang, Shih-Chieh ^{[1
]}

机构：

[1] Natl Tsing Hua Univ, Dept CS, Hsinchu, Taiwan

来源：

2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 | 2007年

关键词：

leakage current; power gating; IR drop;

D O I：

10.1109/DAC.2007.375129

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Power gating is one of the most effective ways to reduce leakage power. In this paper, we introduce a new relationship among Maximum Instantaneous Current, IR drops and sleep transistor networks from a temporal viewpoint. Based on this relationship, we propose an algorithm to reduce the total sizes of sleep transistors in Distributed Sleep Transistor Network designs. On average, the proposed method can achieve 21% reduction in the sleep transistor size.

引用

页码：81 / +

页数：2

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