Test Point Insertion Using Artificial Neural Networks

被引：19
作者：
Sun, Yang [1 ]
Millican, Spencer [1 ]
机构：
[1] Dept Elect & Comp Engn, 341 War Eagle Way, Auburn, AL 36849 USA
来源：
2019 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2019) | 2019年
关键词：
Design for test; test point insertion; built-in self-test; artificial neural networks; DIAGNOSIS;
D O I：
10.1109/ISVLSI.2019.00054
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A method of data collecting, training, and using artificial neural networks (ANNs) for evaluating test point (TP) quality for TP insertion (TPI) is presented in this study. The TPI method analyzes a digital circuit and determines where to insert TPs to improve fault coverage under pseudo-random stimulus, but in contrast to conventional TN algorithms using heuristically-calculated testability measures, the proposed method uses an ANN trained through fault simulation to evaluate a TP's quality. The time of feature extraction is demonstrated to be significantly faster compared to heuristic-based TP evaluation, and the impact of inserted TPs is shown to provide superior stuck-at fault coverage compared to conventional heuristic-based testability analysis.
引用
收藏
页码：254 / 259
页数：6
相关论文
共 17 条
[1]   Neural-network based analog-circuit fault diagnosis using wavelet transform as preprocessor [J].
Aminian, M ;
Aminian, F .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 2000, 47 (02) :151-156
[2]  
Brglez F., 1985, PROC INT S CIRCUITS, P669
[3]  
Brglez F., 1984, P IEEE INT S CIRC SY, V1
[4]  
Briers A. J., 1986, International Test Conference 1986 Proceedings. Testing's Impact on Design and Technology (Cat. No. 86CH2339-0), P274
[5]   TOWARD MASSIVELY PARALLEL AUTOMATIC TEST-GENERATION [J].
CHAKRADHAR, ST ;
BUSHNELL, ML ;
AGRAWAL, VD .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1990, 9 (09) :981-994
[6]   RT-level ITC'99 benchmarks and first ATPG results [J].
Corno, F ;
Reorda, MS ;
Squillero, G .
IEEE DESIGN & TEST OF COMPUTERS, 2000, 17 (03) :44-53
[7]  
Geuzebroek M. J., 2002, P INT TEST C
[8]   Test point insertion for compact test sets [J].
Geuzebroek, MJ ;
van der Linden, JT ;
van de Goor, AJ .
INTERNATIONAL TEST CONFERENCE 2000, PROCEEDINGS, 2000, :292-301
[9]   TEST POINT PLACEMENT TO SIMPLIFY FAULT DETECTION [J].
HAYES, JP ;
FRIEDMAN, AD .
IEEE TRANSACTIONS ON COMPUTERS, 1974, C-23 (07) :727-735
[10]  
Karlik B, 2015, INT J ARTIF INTELL E, V1, P111
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