A 7.2-mW V-Band Frequency Doubler With 14% Total Efficiency in 130-nm SiGe BiCMOS

被引:7
作者
Sutbas, Batuhan [1 ,2 ]
Kahmen, Gerhard [1 ,2 ]
机构
[1] IHP Leibniz Inst Innovat Mikroelekt, D-15236 Frankfurt, Oder, Germany
[2] Brandenburg Tech Univ Cottbus, Inst Elect Engn & Informat Sci, D-03046 Cottbus, Germany
关键词
Inductors; Frequency measurement; Radio frequency; Transformers; Wireless communication; Silicon germanium; Power generation; Frequency doubler (FD); integrated circuit; low-power; millimeter-wave; monolithic transformer; silicon-germanium;
D O I
10.1109/LMWC.2022.3141557
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Low-voltage and low-power frequency multiplier blocks used in millimeter-wave RF frontends suffer from high conversion loss leading to lower overall efficiency. In this letter, an alternative approach in the design of a low-power V-band frequency doubler (FD) block without requiring an additional buffer stage is presented. The transconductance stage of a conventional Gilbert multiplier is replaced by a passive trifilar transformer serving as a power splitting, matching, and biasing network. The switching quad transistors are biased with the lowest possible dc current which still provides a positive conversion gain. Experimental results show that the circuit implemented in a 130-nm SiGe BiCMOS technology achieves 14% total efficiency at 58 GHz for an input power of 0 dBm while consuming only 7.2 mW of dc power. The measured saturated output power is 2 dBm and the measured fundamental rejection ratio (FRR) is 49 dBc. To the best of the authors' knowledge, the lowest power consumption while maintaining a positive conversion gain among high FDs based on silicon is reported.
引用
收藏
页码:579 / 582
页数:4
相关论文
共 15 条
[1]  
Chen GY, 2016, EUR MICROW INTEGRAT, P397, DOI 10.1109/EuMIC.2016.7777575
[2]   A 19.5% Efficiency 51-73-GHz High-Output Power Frequency Doubler in 65-nm CMOS [J].
Chen, Zhilin ;
Yu, Yiming ;
Wu, Yunqiu ;
Liu, Huihua ;
Zhao, Chenxi ;
Kang, Kai .
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, 2019, 29 (12) :818-821
[3]   5 GHz CMOS Quadrature VCO Using Trifilar-Transformer-Coupling Technology [J].
Cheng, Kuang-Wei ;
Tseng, Yan-Ru .
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, 2016, 26 (09) :717-719
[4]  
Cui MQ, 2020, 2020 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT), P40, DOI [10.1109/RFIT49453.2020.9226216, 10.1109/rfit49453.2020.9226216]
[5]   A Ka-Band SiGe Bootstrapped Gilbert Frequency Doubler With 26.2% PAE [J].
Frounchi, Milad ;
Rao, Sunil G. ;
Cressler, John D. .
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, 2018, 28 (12) :1122-1124
[6]   Ultralow Power K-Band Frequency Doubler With Differential Output [J].
Gong, Yue ;
Chen, Jiangbo ;
Du, Likang ;
Gao, Huiyan ;
Liu, Jiabing ;
Wang, Shengjie ;
Li, Huan ;
Song, Chunyi ;
Xu, Zhiwei .
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, 2021, 31 (10) :1162-1165
[7]   Novel miniature and broadband millimeter-wave monolithic star mixers [J].
Kuo, Che-Chung ;
Kuo, Chun-Lin ;
Kuo, Che-Jia ;
Maas, Stephen A. ;
Wang, Huei .
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2008, 56 (04) :793-802
[8]   A Balunless Frequency Multiplier With Differential Output by Current Flow Manipulation [J].
Li, Chun-Hsing ;
Wu, Wei-Min .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 26 (07) :1391-1402
[9]   A Buffer-Less Wideband Frequency Doubler in 45-nm CMOS-SOI With Transistor Multiport Waveform Shaping Achieving 25% Drain Efficiency and 46-89 GHz Instantaneous Bandwidth [J].
Li, Sensen ;
Chi, Taiyun ;
Huang, Tzu-Yuan ;
Huang, Min-Yu ;
Jung, Doohwan ;
Wang, Hua .
IEEE SOLID-STATE CIRCUITS LETTERS, 2019, 2 (04) :25-28
[10]   A low-voltage 5.1-5.8-GHz image-reject downconverter RF IC [J].
Long, JR .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (09) :1320-1328