Automatic generation of customized discrete Fourier transform IPs

被引:0
|
作者
Nordin, G [1 ]
Milder, PA [1 ]
Hoe, JC [1 ]
Püschel, M [1 ]
机构
[1] Carnegie Mellon Univ, Dept Elect & Comp Engn, Pittsburgh, PA 15213 USA
来源
42nd Design Automation Conference, Proceedings 2005 | 2005年
关键词
discrete Fourier transform; IP; design generator; FPGA;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents a parameterized soft core generator for the discrete Fourier transform (DFT). Reusable IN of digital signal processing (DSP) kernels are important time-saving resources in DSP hardware development. Unfortunately, reusable IPs, however optimized, can introduce inefficiencies because they cannot fit the exact requirements of every application context. Given the well-understood and regular computation in DSP kernels, an automatic tool can generate high-quality ready-to-use IPs customized to user-specified cost/performance tradeoffs (beyond basic parameters such as input size and data format). The paper shows that the generated DFT cores can match closely the performance and cost of DFT cores from the Xilinx LogiCore library. Furthermore, the generator can yield DFT cores over a range of different performance/cost tradeoff points that are not available from the library.
引用
收藏
页码:471 / 474
页数:4
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