A Low-Power and Area-Effcient 64-Bit Digital Comparator

A new low-power and area-efficient radix-4 tree-based 64-bit digital comparator is presented in this paper. The proposed design with 64 XOR-XNOR (XE) blocks is custom implemented in 90nm 1.2V multi-threshold technology using Cadence-Virtuoso layout editor. The 64 bit comparator has an area of 1009 mu m(2), a worst case delay of 858 ps, and a power consumption of 898uW at 1G bit/s. The two features, lower power consumption and smaller area compared to other published comparators, make the proposed design most suitable for low-power portable devices. Resource sharing is an important feature for the proposed design. The 64 XE blocks occupy approximately 60% (600 mu m(2)) of the total comparator area and contributes 54% (484 mu W) of the total worst power consumption. The 64 XE blocks can also be used to design XE based 64-bit adders, encryption devices, etc.