Efficient Multiple-Precision Posit Multiplier

被引:0
作者
Zhang, Hao [1 ]
Ko, Seok-Bum [1 ]
机构
[1] Univ Saskatchewan, Dept Elect & Comp Engn, Saskatoon, SK, Canada
来源
2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2021年
关键词
D O I
10.1109/ISCAS51556.2021.9401213
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Posit number system has been recently widely applied in many fields of applications. For different applications, the precision requirements are usually different. In addition, the transprecision computing paradigm, which is proposed for energy efficient computation, even requires different precision in each computation step. To support computations of various precision in a single hardware architecture, in this paper, a unified architecture of multiple-precision posit multiplier is proposed. The proposed posit multiplier supports the commonly used Posit(8, 0), Posit(16, 1), and Posit(32, 2) formats, where one Posit(32, 2), or two parallel Posit(16, 1), or four parallel Posit(8, 0) multiplications can be accomplished each time. Each module of the proposed posit multiplier is carefully tailored for resource sharing among three supported precision formats. Compared to the Posit(32, 2) multiplier, the proposed multiple-precision multiplier adds the support for parallel low-precision posit multiplications with only 12.8% more area and 15.4% more power. The proposed architecture can be used in posit-enabled general-purpose processor designs.
引用
收藏
页数:5
相关论文
共 15 条
  • [1] A SIGNED BINARY MULTIPLICATION TECHNIQUE
    BOOTH, AD
    [J]. QUARTERLY JOURNAL OF MECHANICS AND APPLIED MATHEMATICS, 1951, 4 (02) : 236 - 240
  • [2] Carmichael Z., 2018, P C COGN COMP NEUR
  • [3] Parameterized Posit Arithmetic Hardware Generator
    Chaurasiya, Rohit
    Gustafson, John
    Shrestha, Rahul
    Neudorfer, Jonathan
    Nambiar, Sangeeth
    Niyogi, Kaustav
    Merchant, Farhad
    Leupers, Rainer
    [J]. 2018 IEEE 36TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 2018, : 334 - 341
  • [4] Gustafson John L., 2017, [Supercomputing Frontiers and Innovations, Supercomputing Frontiers and Innovations], V4, P71
  • [5] IEEE Computer Society, 2019, IEEE standard for floating-point arithmetic, DOI [10.1109/IEEESTD.2019.8859679, DOI 10.1109/IEEESTD.2008.4610935, 10.1109/IEEESTD.2019.8766229, DOI 10.1109/IEEESTD.2019.8766229, 10.1109/IEEESTD.2017.8091139]
  • [6] Jain R., 2020, CLAR INET RISC V BAS, V1, P1
  • [7] PACoGen: A Hardware Posit Arithmetic Core Generator
    Jaiswal, Manish Kumar
    So, Hayden K-H
    [J]. IEEE ACCESS, 2019, 7 : 74586 - 74601
  • [8] Architecture Generator for Type-3 Unum Posit Adder/Subtractor
    Jaiswal, Manish Kumar
    So, Hayden K. -H
    [J]. 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2018,
  • [9] Posits as an alternative to floats for weather and climate models
    Klower, Milan
    Duben, Peter D.
    Palmer, Tim N.
    [J]. CONFERENCE FOR NEXT GENERATION ARITHMETIC 2019 (CONGA), 2019,
  • [10] A Reduced-Order Generalized Proportional Integral Observer-Based Resonant Super-Twisting Sliding Mode Control for Grid-Connected Power Converters
    Lu, Jinghang
    Savaghebi, Mehdi
    Ghias, Amer M. Y. M.
    Hou, Xiaochao
    Guerrero, Josep M.
    [J]. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2021, 68 (07) : 5897 - 5908