The Laplace Microarchitecture for Tracking Data Uncertainty and Its Implementation in a RISC-V Processor

被引:0
|
作者
Tsoutsouras, Vasileios [1 ,2 ]
Kaparounakis, Orestis [1 ]
Bilgin, Bilgesu [2 ]
Samarakoon, Chatura [2 ]
Meech, James [2 ]
Heck, Jan [2 ]
Stanley-Marbell, Phillip [1 ,2 ]
机构
[1] Signaloid, Cambridge, England
[2] Univ Cambridge, Cambridge, England
来源
PROCEEDINGS OF 54TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, MICRO 2021 | 2021年
基金
英国工程与自然科学研究理事会;
关键词
uncertainty tracking; distributional representations; arithmetic on distributions; RISC-V; FUZZY; ARCHITECTURE;
D O I
10.1145/3466752.3480131
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We present Laplace, a microarchitecture for tracking machine representations of probability distributions paired with architectural state. We present two newmethods for in-processor distribution representations which are approximations of probability distributions just as floating-point number representations are approximations of real-valued numbers. Laplace executes unmodified RISC-V binaries and can track uncertainty through them. We present two sets of ISA extensions to provide a mechanism to initialize distributional information in the microarchitecture and to allow applications to query statistics of the distributional information without exposing the uncertainty representations above the ISA. We evaluate the accuracy and performance of Laplace using a suite of 21 benchmarks spanning domains ranging from variational quantum algorithms and sensor data processing to materials properties modeling. Monte Carlo simulation on the benchmarks requires 2 076x more instructions on average (and up to 21 343x in some cases) to achieve the same accuracy that Laplace can achieve in a single execution. Compared to state-of-the-art alternatives to Monte Carlo, Laplace achieves an average 1.3x accuracy improvement versus PaCAL [22] and more than 4.6x accuracy improvement versus the method used by the NIST Uncertainty Machine [26], quantified using the Wasserstein distance to Monte Carlo. Unlike existing methods for uncertainty tracking which require software to be rewritten in a domain-specific language or extensive source-level changes, Laplace achieves all of these benefits while requiring no changes to existing binaries in order to track uncertainty through them, with only minimal changes required to get uncertainty information into the microarchitecture. We have deployed an implementation of Laplace as a commercial product in the form of a cloud-accessible virtual machine.
引用
收藏
页码:1254 / 1269
页数:16
相关论文
共 50 条
  • [41] A Custom Designed RISC-V ISA Compatible Processor for SoC
    Sharat, Kavya
    Bandishte, Sumeet
    Varghese, Kuruvilla
    Bharadwaj, Amrutur
    VLSI DESIGN AND TEST, 2017, 711 : 570 - 577
  • [42] RISC-HD: Lightweight RISC-V Processor for Efficient Hyperdimensional Computing Inference
    Taheri, Farhad
    Bayat-Sarmadi, Siavash
    Hadayeghparast, Shahriar
    IEEE INTERNET OF THINGS JOURNAL, 2022, 9 (23) : 24030 - 24037
  • [43] An integrated machine code monitor for a RISC-V processor on an FPGA
    Hiroaki Kaneko
    Akinori Kanasugi
    Artificial Life and Robotics, 2020, 25 : 427 - 433
  • [44] RISCALAR: A Cycle-Approximate, Parametrisable RISC-V Microarchitecture Explorer & Simulator
    Mendes, Josiah
    Panicker, Rajesh C.
    2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024, 2024,
  • [45] Microarchitecture based RISC-V Instruction Set Architecture for Low Power Application
    Deepika, R.
    Priyadharsini, S. M. Gopika
    Malar, M. Muthu
    Anand, I. Vivek
    JOURNAL OF PHARMACEUTICAL NEGATIVE RESULTS, 2022, 13 : 362 - 371
  • [46] Design and Implementation of a RISC V Processor on FPGA
    Poli, Ludovico
    Saha, Sangeet
    Zhai, Xiaojun
    Mcdonald-Maier, Klaus D.
    2021 17TH INTERNATIONAL CONFERENCE ON MOBILITY, SENSING AND NETWORKING (MSN 2021), 2021, : 161 - 166
  • [47] McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework
    Zhai, Jianwang
    Bai, Chen
    Zhu, Binwu
    Cai, Yici
    Zhou, Qiang
    Yu, Bei
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 42 (01) : 243 - 256
  • [48] Design and implementation of a synchronous Hardware Performance Monitor fora RISC-V space-oriented processor
    Arribas, Miguel Jimenez
    Hellin, Agustin Martinez
    Mateo, Manuel Prieto
    del Rio, Ivan Gamino
    Gallego, Andrea Fernandez
    Polo, oscar Rodriguez
    da Silva, Antonio
    Parra, Pablo
    Sanchez, Sebastian
    MICROPROCESSORS AND MICROSYSTEMS, 2025, 112
  • [49] BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration
    Bai, Chen
    Sun, Qi
    Zhai, Jianwang
    Ma, Yuzhe
    Yu, Bei
    Wong, Martin D. F.
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2024, 29 (01)
  • [50] A Time Series Data Compression Co-processor Based on RISC-V Custom Instructions
    Du, Peiran
    Cai, Zhaohui
    ALGORITHMS AND ARCHITECTURES FOR PARALLEL PROCESSING, ICA3PP 2023, PT I, 2024, 14487 : 439 - 454