The Laplace Microarchitecture for Tracking Data Uncertainty and Its Implementation in a RISC-V Processor

被引:0
|
作者
Tsoutsouras, Vasileios [1 ,2 ]
Kaparounakis, Orestis [1 ]
Bilgin, Bilgesu [2 ]
Samarakoon, Chatura [2 ]
Meech, James [2 ]
Heck, Jan [2 ]
Stanley-Marbell, Phillip [1 ,2 ]
机构
[1] Signaloid, Cambridge, England
[2] Univ Cambridge, Cambridge, England
来源
PROCEEDINGS OF 54TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, MICRO 2021 | 2021年
基金
英国工程与自然科学研究理事会;
关键词
uncertainty tracking; distributional representations; arithmetic on distributions; RISC-V; FUZZY; ARCHITECTURE;
D O I
10.1145/3466752.3480131
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We present Laplace, a microarchitecture for tracking machine representations of probability distributions paired with architectural state. We present two newmethods for in-processor distribution representations which are approximations of probability distributions just as floating-point number representations are approximations of real-valued numbers. Laplace executes unmodified RISC-V binaries and can track uncertainty through them. We present two sets of ISA extensions to provide a mechanism to initialize distributional information in the microarchitecture and to allow applications to query statistics of the distributional information without exposing the uncertainty representations above the ISA. We evaluate the accuracy and performance of Laplace using a suite of 21 benchmarks spanning domains ranging from variational quantum algorithms and sensor data processing to materials properties modeling. Monte Carlo simulation on the benchmarks requires 2 076x more instructions on average (and up to 21 343x in some cases) to achieve the same accuracy that Laplace can achieve in a single execution. Compared to state-of-the-art alternatives to Monte Carlo, Laplace achieves an average 1.3x accuracy improvement versus PaCAL [22] and more than 4.6x accuracy improvement versus the method used by the NIST Uncertainty Machine [26], quantified using the Wasserstein distance to Monte Carlo. Unlike existing methods for uncertainty tracking which require software to be rewritten in a domain-specific language or extensive source-level changes, Laplace achieves all of these benefits while requiring no changes to existing binaries in order to track uncertainty through them, with only minimal changes required to get uncertainty information into the microarchitecture. We have deployed an implementation of Laplace as a commercial product in the form of a cloud-accessible virtual machine.
引用
收藏
页码:1254 / 1269
页数:16
相关论文
共 50 条
  • [1] The Laplace Microarchitecture for Tracking Data Uncertainty
    Tsoutsouras, Vasileios
    Kaparounakis, Orestis
    Samarakoon, Chatura
    Bilgin, Bilgesu
    Meech, James
    Heck, Jan
    Stanley-Marbell, Phillip
    IEEE MICRO, 2022, 42 (04) : 78 - 86
  • [2] An Implementation of a Pattern Matching Accelerator on a RISC-V Processor
    Takayama, Riku
    Tada, Jubee
    2022 TENTH INTERNATIONAL SYMPOSIUM ON COMPUTING AND NETWORKING WORKSHOPS, CANDARW, 2022, : 273 - 275
  • [3] IndiRA: Design and Implementation of a Pipelined RISC-V Processor
    Tiwari, Ankita
    Guha, Prithwijit
    Trivedi, Gaurav
    Gupta, Nitesh
    Jayaraj, Navneeth
    Pidanic, Jan
    2023 33RD INTERNATIONAL CONFERENCE RADIOELEKTRONIKA, RADIOELEKTRONIKA, 2023,
  • [4] Design of a Convolutional Neural Network Instruction Set Based on RISC-V and Its Microarchitecture Implementation
    Jiao, Qiang
    Hu, Wei
    Wen, Yuan
    Dong, Yong
    Li, Zhenhao
    Gan, Yu
    ALGORITHMS AND ARCHITECTURES FOR PARALLEL PROCESSING, ICA3PP 2020, PT II, 2020, 12453 : 82 - 96
  • [5] Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability
    Sreekumar, Aswin
    Shankar, Bolupadra Sai
    Reddy, B. Naresh Kumar
    INTEGRATION-THE VLSI JOURNAL, 2025, 100
  • [6] Maxpool operator for RISC-V processor
    Nevezi-Strango, David
    Rotar, Danut
    Valcan, Sorin
    Gaianu, Mihail
    2023 25TH INTERNATIONAL SYMPOSIUM ON SYMBOLIC AND NUMERIC ALGORITHMS FOR SCIENTIFIC COMPUTING, SYNASC 2023, 2023, : 246 - 250
  • [7] Design and Implementation of a Smart Home System Based on the RISC-V Processor
    Lu, Liangliang
    Zhang, Ming
    He, Dingxin
    PROCEEDINGS OF 2020 IEEE 2ND INTERNATIONAL CONFERENCE ON CIVIL AVIATION SAFETY AND INFORMATION TECHNOLOGY (ICCASIT), 2020, : 300 - 304
  • [8] An Implementation of a World Grid Square Codes Generator on a RISC-V Processor
    Watanabe, Rei
    Tada, Jubee
    Sato, Keiichi
    Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021, 2021, : 309 - 312
  • [9] Implementation of Hardware Trace Buffer Module for RISC-V Processor Core
    Shveida, Bohdan
    Marcinek, Krzysztof
    Pleskacz, Witold A.
    2024 31ST INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEM, MIXDES 2024, 2024, : 110 - 113
  • [10] RISC-V2: A Scalable RISC-V Vector Processor
    Patsidis, Kariofyllis
    Nicopoulos, Chrysostomos
    Sirakoulis, Georgios Ch
    Dimitrakopoulos, Giorgos
    2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2020,