Bit-Line Decoupled SRAM for Reducing Read Delays in Near Threshold Voltage Operations

As static random access memory (SRAM) takes a dominant portion in current system on a chip (SoC), lowering the supply voltage of SRAM would effectively reduce the overall power consumption of SoC. However, lowering SRAM supply voltage causes large read delays and malfunctions. In this paper, we present a bit-line (BL) decoupled SRAM structure that can efficiently provide fast and accurate read operation in near threshold voltage operations. The improvement in read operation is obtained by reducing bit-line parasitic capacitance with decoupling between bit-line and data node in memory cell in the proposed SRAM. The BL decoupled SRAM implementation using 28nm CMOS process shows that the average and standard deviation of read delay are reduced by 40.8% and 56.3%, respectively, compared to conventional SRAM under 0.5 V.