High-speed, spurious-free sequential phase frequency detector and dual-modulus prescalers for RF frequency synthesis

被引：3

作者：

Sié, M ^{[1
]}

Gilles, C ^{[1
]}

Tournier, É ^{[1
]}

Robert, P ^{[1
]}

Graffeuil, J ^{[1
]}

机构：

[1] CNRS, LAAS, F-31077 Toulouse, France

来源：

2003 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS | 2003年

关键词：

D O I：

10.1109/RFIC.2003.1214038

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Original integrated 22-GHz dual-modulus static frequency dividers (4/5) realized in a Silicon Germanium BiCMOS technology dedicated for high volume production are presented. They operate at low bias voltage (3.3 V) and provide balanced output signals on 50 ohm loads. An optimized digital tri-state phase/frequency detector (PFD) is also reported. A new proposed architecture and original logic approach translate into excellent spurious immunity and high-speed detection: the proposed structure has the advantage to cancel the spurious which are present whatever the state of the comparator. Such features make these versatile circuits blocks essential for low noise, high-frequency PLL systems.

引用

页码：679 / 682

页数：4

共 6 条

[1] Design considerations in a BiCMOS dual-modulus prescaler [J].

Dülger, F ;

Sánchez-Sinencio, E ;

Bellaouar, A .

2002 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS, 2002, :177-180

[2]

MASINI L, 2002, EUROPEAN MICROWAVE W, P323

[3]

Razavi B, 2011, RF Microelectronics, V2nd

[4]

Rohde U. L, 1983, DIGITAL PLL FREQUENC

[5] High-speed dual-modulus prescaler architecture for programmable digital frequency dividers [J].

Tournier, É ;

Sié, M ;

Graffeuil, J .

ELECTRONICS LETTERS, 2001, 37 (24) :1433-1434

[6] A low-power 20 GHz static frequency divider with programmable input sensitivity [J].

Vaucher, CS ;

Apostolidou, M .

2002 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS, 2002, :235-238

← 1 →