Automatic test generation algorithms for analogue circuits

被引：15
作者：
Soma, M
机构：
[1] Department of Electrical Ensrineerinc, University of Washington, Box 352500, Seattle
来源：
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS | 1996年 / 143卷 / 06期
关键词：
automatic test generation; analogue circuits;
D O I：
10.1049/ip-cds:19960898
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The author reviews the recently published automatic test generation algorithms for analogue circuits, focusing on their applicability to specific circuit classes, limitations in more general applications and possible improvements. Selected new test generation paradigms, involving design-for-test and BIST techniques, are also discussed to indicate future directions in test generation.
引用
收藏
页码：366 / 373
页数：8
相关论文
共 59 条
[1]  
ABDERRAHMAN A, 1995, IEEE INT MIX SIGN TE
[2]  
ARABI K, 1994, IEEE INT C COMP AID
[3]  
ARABI K, 1996, IEEE VLSI TEST S PRI
[4]   Analog testing with time response parameters [J].
Balivada, A ;
Chen, J ;
Abraham, JA .
IEEE DESIGN & TEST OF COMPUTERS, 1996, 13 (02) :18-25
[5]  
BALIVADA A, 1995, IEEE INT MIX SIGN TE
[6]  
BEASLEY JS, 1993, IEEE INT TEST C WASH
[7]   MULTIPLE-FAULT ANALOG CIRCUIT TESTING BY SENSITIVITY ANALYSIS [J].
BENHAMIDA, N ;
KAMINSKA, B .
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 1993, 4 (03) :231-243
[8]  
BISHOP AJ, 1994, INT WORKSH DEF FAULT
[9]   DESIGN-FOR-TEST STRUCTURE TO FACILITATE TEST VECTOR APPLICATION WITH LOW PERFORMANCE LOSS IN NON-TEST MODE [J].
BRATT, AH ;
HARVEY, RJ ;
DOREY, AP ;
RICHARDSON, AMD .
ELECTRONICS LETTERS, 1993, 29 (16) :1438-1440
[10]  
CORSI F, 1993, EUR TEST C ROTT THE
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