A novel SCR ESD protection structure with low-loading and latchup immunity for high-speed I/O pad

被引：6
|
作者：
Lai, CS [1 ]
Liu, MH [1 ]
Su, S [1 ]
Lu, TC [1 ]
机构：
[1] MXIC, Silicon Lab, Special Device Modeling Dept, Hsinchu, Taiwan
来源：
2003 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS | 2003年
关键词：
D O I：
10.1109/VTSA.2003.1252557
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A novel SCR device "Latchup-free gate-couple LVTPSCR (LFGCPSCR)" has been proposed to act as an efficient ESD protection device with low loading effect. With the proper control circuit, the trigger voltage under normal operation can be high up to 14 V, providing excellent immunity to Latchup. Under ESD events, this novel SCR device could trigger fast and provide an effective discharging path for ESD.
引用
收藏
页码：80 / 83
页数：4
相关论文
共 50 条
  • [31] Design of Dual-Directional SCR Structure With High Holding Voltage and Low Dynamic Resistance for High Voltage ESD Protection
    Do, Kyoung-Il
    Jung, Jin-Woo
    Song, Jooyoung
    Jeon, Chan-Hee
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2023, 70 (09) : 4509 - 4517
  • [32] Optimization on Layout Style of ESD Protection Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits
    Yeh, Chih-Ting
    Ker, Ming-Dou
    Liang, Yung-Chih
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2010, 10 (02) : 238 - 246
  • [33] Layout Optimization on ESD Diodes for Giga-Hz RF and High-Speed I/O Circuits
    Yeh, Chih-Ting
    Liang, Yung-Chih
    Ker, Ming-Dou
    2010 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AUTOMATION AND TEST (VLSI-DAT), 2010, : 241 - 244
  • [34] Low-Loss I/O Pad With ESD Protection for K/Ka-Bands Applications in the Nanoscale CMOS Process
    Peng, Bo-Wei
    Lin, Chun-Yu
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2018, 65 (10) : 1475 - 1479
  • [35] ESD protection design for high-speed I/O interface of stub series terminated logic (SSTL) in a 0.25-μm salicided CMOS process
    Ker, MD
    Chuang, CH
    IPFA 2004: PROCEEDINGS OF THE 11TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS, 2004, : 217 - 220
  • [36] A fail-safe ESD protection circuit with 230 fF linear capacitance for high-speed/high-precision 0.18 μm CMOS I/O application
    Lin, J
    Duvvury, C
    Haroun, B
    Oguzman, I
    Somayaji, A
    INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, 2002, : 349 - 352
  • [37] A novel on-chip electrostatic discharge (ESD) protection with common discharge line for high-speed CMOS LSI's
    Narita, K
    Horiguchi, Y
    Fujii, T
    Nakamura, K
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1997, 44 (07) : 1124 - 1130
  • [38] Novel High Holding Voltage SCR with Embedded Carrier Recombination Structure for Latch-up Immune and Robust ESD Protection
    Zhuo Wang
    Zhao Qi
    Longfei Liang
    Ming Qiao
    Zhaoji Li
    Bo Zhang
    Nanoscale Research Letters, 2019, 14
  • [39] A novel high-speed, low-offset, loading condition-adaptable voltage buffer
    Neag, Marius
    Fazakas, Albert
    Festila, Lelia
    2006 INTERNATIONAL CONFERENCE ON APPLIED ELECTRONICS, 2006, : 121 - 124
  • [40] Design of High -Reliability LDO regulator with SCR based ESD Protection circuit using dual buffer structure for low -voltage applications
    Kwon, Sang Wook
    Lee, Byung Seok
    Hwan, Baek Seung
    Koo, Yong Seo
    2022 6TH EUROPEAN CONFERENCE ON ELECTRICAL ENGINEERING & COMPUTER SCIENCE, ELECS, 2022, : 59 - 65
12345