A novel SCR ESD protection structure with low-loading and latchup immunity for high-speed I/O pad

被引：6
|
作者：
Lai, CS [1 ]
Liu, MH [1 ]
Su, S [1 ]
Lu, TC [1 ]
机构：
[1] MXIC, Silicon Lab, Special Device Modeling Dept, Hsinchu, Taiwan
来源：
2003 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS | 2003年
关键词：
D O I：
10.1109/VTSA.2003.1252557
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A novel SCR device "Latchup-free gate-couple LVTPSCR (LFGCPSCR)" has been proposed to act as an efficient ESD protection device with low loading effect. With the proper control circuit, the trigger voltage under normal operation can be high up to 14 V, providing excellent immunity to Latchup. Under ESD events, this novel SCR device could trigger fast and provide an effective discharging path for ESD.
引用
收藏
页码：80 / 83
页数：4
相关论文
共 50 条
  • [1] Novel gate-coupled SCR ESD protection structure with high latchup immunity for high-speed I/O pad
    Lai, CH
    Liu, MH
    Su, S
    Lu, TC
    Pan, S
    IEEE ELECTRON DEVICE LETTERS, 2004, 25 (05) : 328 - 330
  • [2] A Novel SCR Structure Integrated with Power Clamp for ESD Protection at I/O Pad
    Fan, Hang
    Jiang, Lingli
    Zhang, Bo
    2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012), 2012, : 1223 - 1225
  • [3] Novel Topological Layout for ESD protection for high-speed I/O applications
    Ma, Qinling
    Liang, Hailian
    2022 INTERNATIONAL EOS/ESD SYMPOSIUM ON DESIGN AND SYSTEM (IEDS), 2022,
  • [4] Resistor-Triggered SCR Device for ESD Protection in High-Speed I/O Interface Circuits
    Lin, Chun-Yu
    Chen, Chun-Yu
    IEEE ELECTRON DEVICE LETTERS, 2017, 38 (06) : 712 - 715
  • [5] FinFET SCR Structure Optimization for High-Speed Serial Links ESD Protection
    Chu, Li-Wei
    Chang, Yi-Feng
    Su, Yu-Ti
    Chen, Kuo-Ji
    Song, Ming-Hsiang
    Lee, Jam-Wem
    2016 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2016,
  • [6] An SCR-Incorporated BJT Device for Robust ESD Protection With High Latchup Immunity in High-Voltage Technology
    Huang, Chih-Yao
    Chiu, Fu-Chien
    Chen, Quo-Ker
    Lai, Ming-Fang
    Tseng, Jen-Chou
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2012, 12 (01) : 113 - 123
  • [7] Transient Response of ESD Protection Devices for a High-Speed I/O Interface
    Zhou, Jianchi
    Xu, Yang
    Bub, Sergej
    Holland, Steffen
    Meiguni, Javad Soleiman
    Pommerenke, David
    Beetner, Daryl G.
    IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, 2022, 64 (04) : 907 - 914
  • [8] Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications
    Yeh, Chih-Ting
    Ker, Ming-Dou
    MICROELECTRONICS RELIABILITY, 2012, 52 (06) : 1020 - 1030
  • [9] High-Robustness and Low-Capacitance Silicon-Controlled Rectifier for High-Speed I/O ESD Protection
    Cui, Qiang
    Salcedo, Javier A.
    Parthasarathy, Srivatsan
    Zhou, Yuanzhong
    Liou, Juin J.
    Hajjar, Jean J.
    IEEE ELECTRON DEVICE LETTERS, 2013, 34 (02) : 178 - 180
  • [10] On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology
    Chen, Jie-Ting
    Lin, Chun-Yu
    Ker, Ming-Dou
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017, 64 (10) : 3979 - 3985
12345