Power-Aware High-Level Synthesis With Clock Skew Management

被引:1
作者
Yeh, Tung-Hua [1 ]
Wang, Sying-Jyan [1 ]
机构
[1] Natl Chung Hsing Univ, Taichung 40227, Taiwan
关键词
Clock-skew scheduling; high-level synthesis; low-power design;
D O I
10.1109/TVLSI.2010.2091292
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
An effective clock-skew scheduling scheme in the high-level synthesis process targeted for power and speed optimization is presented. The proposed scheme has the following distinctive features: 1) a clock-skew management algorithm that selects a minimum set of clock phases to achieve the optimization goals is developed; 2) the effect of module binding in high-level synthesis was not considered in previous studies, which may lead to designs with timing violation; a discussion on how to model the effect of module binding is provided; 3) a heuristic low-power module binding algorithm that provides near-optimal results quickly is proposed; and 4) a technique called reallocation is proposed to exploit all available skews and thus maximize the capability of clock-skew scheduling. Experimental results show that, on the average, 48% power reduction is achieved by the proposed method. At most five clock phases are required, while in most cases two to four clock phases are sufficient.
引用
收藏
页码:167 / 171
页数:5
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