A high-speed four-phase clock generator for low-power on-chip SerDes applications

被引：3
|
作者：
Zid, Mounir [1 ]
Scandurra, Alberto [2 ]
Tourki, Rached [1 ]
Pistritto, Carlo [2 ]
机构：
[1] Fac Sci Monastir, Elect & MicroElect Lab, Monastir 5000, Tunisia
[2] STMicroelectronics, OCCS, Catania, Italy
来源：
MICROELECTRONICS JOURNAL | 2011年 / 42卷 / 09期
关键词：
Multiphase clocks; Four-phase clock generator; High-speed devices; Parallel architectures; Low-power architectures; SerDes;
D O I：
10.1016/j.mejo.2011.06.012
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this work we present a low-power, low-area and high-speed fully CMOS quadrature clock generator for on-chip SerDes applications. The device utilizes a couple of differential prescalers for high speed frequency division and four duty cycle adjusters to set the duty cycle of the produced clock signals at 50% of the clock period. The circuit was implemented with the STMicroelectronics 65 nm process technology using only 125 transistors and it occupies an active area of under 2.34 mu m(2). With a power supply of 1.1 V the complete circuit consumes 89.56 mu W at room temperature. (C) 2011 Elsevier Ltd. All rights reserved.
引用
收藏
页码：1049 / 1056
页数：8
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