DeepTrans - A model-based approach to functional verification of address translation mechanisms

被引：8

作者：

Adir, A ^{[1
]}

Emek, R ^{[1
]}

Katz, Y ^{[1
]}

Koyfman, A ^{[1
]}

机构：

[1] IBM Res Lab, Haifa, Israel

来源：

4TH INTERNATIONAL WORKSHOP ON MICROPROCESSOR TEST AND VERIFICATION: COMMON CHALLENGES AND SOLUTIONS, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/MTV.2003.1250255

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a new test case generation technology, specifically targeted at verifying systems that include address translation mechanisms. The ever-growing demand for performance makes these mechanisms more complex, thereby increasing the risk of bugs and increasing the need for such technology. DeepTrans is a package that provides model-based test generation capabilities to verify translation mechanisms based on a modeling language. The modeling language includes constructs for describing the address translation process, commonly used translation resources, and architecture rules related to translation. DeepTrans is currently used by two different IBM test generators.

引用

页码：3 / 6

页数：4

共 9 条

[1] Generating concurrent test-programs with collisions for multi-processor verification [J].

Adir, A ;

Shurek, G .

SEVENTH IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS, 2002, :77-82

[2]

AHARON A, 1995, DES AUT CON, P279, DOI 10.1109/DAC.1995.249960

[3]

AHARON A, 1994, INNOVATION APPL ARTI

[4]

Bentley B, 2001, DES AUT CON, P244

[5] Using a constraint satisfaction formulation and solution techniques for random test program generation [J].

Bin, E ;

Emek, R ;

Shurek, G ;

Ziv, A .

IBM SYSTEMS JOURNAL, 2002, 41 (03) :386-402

[6] X-Gen: A random test-case generator for systems and SOCS [J].

Emek, R ;

Jaeger, I ;

Naveh, Y ;

Bergman, G ;

Aloni, G ;

Katz, Y ;

Farkash, M ;

Dozoretz, I ;

Goldin, A .

SEVENTH IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS, 2002, :145-150

[7] Functional verification methodology for microprocessors using the Genesys test-program generator - Application to the x86 microprocessors family [J].

Fournier, L ;

Arbetman, Y ;

Levinger, M .

DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS, 1999, :434-441

[8]

KUMAR V, 1992, AI MAG, V13, P32

[9]

Taylor S, 1998, 1998 DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, P638, DOI 10.1109/DAC.1998.724549

← 1 →