A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors

被引：20
作者：
Segura, J
DeBenito, C
Rubio, A
Hawkins, CF
机构：
[1] UNIV POLITECN CATALUNA,DEPT ELECT ENGN,BARCELONA 08028,SPAIN
[2] UNIV NEW MEXICO,DEPT ELECT & COMP ENGN,ALBUQUERQUE,NM 87131
来源：
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | 1996年 / 8卷 / 03期
关键词：
gate oxide short; physical defects; fault modeling;
D O I：
10.1007/BF00133386
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The characteristics of devices with gate oxide short defects are investigated for both n-MOS and p-MOS transistors. Experimental results obtained from real and design induced gate oxide shorts are presented analyzing the defect-induced conduction mechanisms that determine the transistor behavior. It is shown that three variables (defect location, transistor type and gate polysilicon doping type) influence the characteristics of a defective device. Of interest is the prediction and observation of a particular gate oxide short type that can cause latchup. An electrical model is proposed and compared with experimental data. Such a model is developed to be used in electrical CAD environments without introducing a penalty in the simulation time.
引用
收藏
页码：229 / 239
页数：11
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