Engine for Characterization of Defects, Overlay and Critical Dimension Control for Double Exposure Processes for Advanced Logic Nodes

被引：5

作者：

Holmes, Steven ^{[1
]}

Koay, Chiew-seng ^{[1
]}

Petrillo, Karen ^{[1
]}

Chen, Kuang-Jung ^{[1
]}

Colburn, Matthew E. ^{[1
]}

Cantone, Jason ^{[2
]}

Ueda, Kenichi ^{[2
]}

Metz, Andrew ^{[3
]}

Dunn, Shannon ^{[3
]}

van Dommelen, Youri ^{[4
]}

Crouse, Michael ^{[4
]}

Galloway, Judy ^{[4
]}

Schmitt-Weaver, Emil ^{[4
]}

Jiang, Aiqin ^{[4
]}

Routh, Robert ^{[4
]}

Tang, Cherry ^{[5
]}

Slezak, Mark ^{[6
]}

Kini, Sumanth ^{[7
]}

Dibiase, Tony ^{[7
]}

机构：

[1] IBM Corp, 257 Fuller Rd, Albany, NY 12203 USA

[2] Tokyo Elect Amer Inc, Hopewell Jct, NY 12533 USA

[3] Tokyo Elect Technol Ctr, Amer LLC, Albany, NY 12203 USA

[4] ASML, Albany, NY 12203 USA

[5] JSR Micro Inc, Albany, NY 12203 USA

[6] JSR Micro Inc, Sunnyvale, CA 94089 USA

[7] KLA, Albany, NY 12203 USA

来源：

ADVANCES IN RESIST MATERIALS AND PROCESSING TECHNOLOGY XXVI | 2009年 / 7273卷

关键词：

Pitch-split; double patterning; defectivity; overlay;

D O I：

10.1117/12.828483

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

As our ability to scale lithographic dimensions via reduction of actinic wavelength and increase of numerical aperture (NA) comes to an end, we need to find alternative methods of increasing pattern density. Double-Patterning techniques have attracted widespread interest for enabling further scaling of semiconductor devices. We have developed DE2 (develop/etch/develop/etch) and DETO (Double-Expose-Track-Optimized) methods for producing pitch-split patterns capable of supporting 16 and 11-nm node semiconductor devices. The IBM Alliance has established a DETO baseline in collaboration with KT, TEL, ASML and JSR to evaluate commercially available resist-on-resist systems. In this paper we will describe our automated engine for characterizing defectivity, line width and overlay performance for our DETO process.

引用

页数：13

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