Highly Parallel and Fully Reused H.264/AVC High Profile Intra Predictor Generation Engine for Super Hi-Vision 4kx4k@60 fps

被引:0
作者
Huang, Yiqing [1 ]
Jin, Xiaocong [1 ]
Zhou, Jin [1 ]
Su, Jia [1 ]
Ikenaga, Takeshi [1 ]
机构
[1] Waseda Univ, IPS, Kitakyushu, Fukuoka 8080135, Japan
来源
IEICE TRANSACTIONS ON ELECTRONICS | 2011年 / E94C卷 / 04期
关键词
H.264/AVC; infra prediction; hardware architecture; super hi-vision; MODE DECISION ALGORITHM; COMPLEXITY REDUCTION; DESIGN; ENCODER;
D O I
10.1587/transele.E94.C.428
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
One high profile intra predictor generation engine is proposed in this paper. Firstly, hardware level algorithm optimization for intra 8 x 8 (I8MB) mode is introduced. The original candidate pixels for generating prediction samples of I8MB are replaced with boundary pixels of intra 4 x 4 (I4MB) blocks. Based on this adoption, full data reuse between predictors of I4MB and filtered samples of I8MB can be achieved with almost no quality loss. Secondly, one lossless two-4 x 4-block based parallel predictor generation flow is proposed. The original predictor generation flow is optimized from 16 stages to 10 stages for I4MB and Intra 16 x 16 (I16MB), which saves 37.5% processing cycles. For I8MB, similar methodology with different processing order of 4 x 4 scaled blocks is introduced. Thirdly, fully utilized hardwired engines for I4MB, I16MB and I8MB are proposed in this paper. Except DC (direct current) and plane modes, full data reuse among all intra modes of high profile can be achieved. Fourthly, for DC mode, one combined predictor generation process is introduced and predictor generation of I16MB's DC mode is merged into the process of I4MB's DC mode. Moreover, by configuring proposed hardwired engines, predictor generation of I16MB's plane mode and chrominance plane mode can be accomplished with only 50% cycles of original design. Totally, when compared with original full-mode design and latest dynamic mode reused design, the proposed predictor generation engine can achieve 89.5% and 73.2% saving of processing cycles. respectively. Synthesized by TSMC 0.18 mu m technology under worst work conditions (1.62 V, 125 degrees C), with 380 MHz and 37.2k gates, the proposed design can handle real-time high profile intra predictor generation of Super Hi-Vision 4k x 4k@60 fps. The maximum work frequency of our design under worst condition is 468 MHz.
引用
收藏
页码:428 / 438
页数:11
相关论文
共 20 条
  • [1] [Anonymous], 1996, 138182 ISOIEC
  • [2] [Anonymous], 1998, Video coding for low bitrate communication
  • [3] Berger T, 1971, Rate Distortion Theory. A Mathematical Basis for Data Compression
  • [4] A Dynamic Quality-Adjustable H.264 Video Encoder for Power-Aware Video Applications
    Chang, Hsiu-Cheng
    Chen, Jia-Wei
    Wu, Bing-Tsung
    Su, Ching-Lung
    Wang, Jinn-Shyan
    Guo, Jiun-In
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2009, 19 (12) : 1739 - 1754
  • [5] Highly Parallel Rate-Distortion Optimized Intra-Mode Decision on Multicore Graphics Processors
    Cheung, Ngai-Man
    Au, Oscar C.
    Kung, Man-Cheung
    Wong, Peter H. W.
    Liu, Chun Hung
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2009, 19 (11) : 1692 - 1703
  • [6] CHUANG T, 2007, PCS 07 PICT COD S NO
  • [7] Macroblock Feature Based Complexity Reduction for H.264/AVC Motion Estimation
    Huang, Yiqing
    Liu, Qin
    Ikenaga, Takeshi
    [J]. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2008, E91A (10) : 2934 - 2944
  • [8] Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder
    Huang, YW
    Hsieh, BY
    Chen, TC
    Chen, LG
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2005, 15 (03) : 378 - 401
  • [9] Analysis and complexity reduction of multiple reference frames motion estimation in H.264/AVC
    Huang, YW
    Hsieh, BY
    Chien, SY
    Ma, SY
    Chen, LG
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2006, 16 (04) : 507 - 522
  • [10] HUANG YW, 2005, IEEE INT SOL STAT CI, P128, DOI DOI 10.1109/ISSCC.2005.1493902