Computer-aided inspection of some design rules of integrated circuit layers

The visual inspection algorithms for verification of industrial design rules of integrated circuits are proposed. The algorithms include segmentation of images of layout with subsequent extraction of typical patterns on these images for defects localization. The unique feature of the technological rules is performed at different stages of processing. Thus a time-consuming procedure of image matching with the purpose of localization of defects is performed only for some images from the whole image set. The inspection algorithms are included in the system of metallization layers processing, which is applied both for layout reconstruction of integrated circuits and for the inspection of its manufacture.