Retargetable and tuneable code generation for high performance DSP

An approach of intelligent retargetable tuncable compiler is introduced to overcome the gap between hardware and software development and to increase performance of embedded systems by enhancing their instruction-level-parallelism. It focuses on high-level model and knowledgeable treatment of code generation where knowledge about target microprocessor architecture and human-level heuristics are integrated into compiler production expert system. XML is used as platform-independent representation of data and knowledge for design process. Structure of an experimental compiler which is developed to support the approach for microprocessors with irregular architecture like DSP and VLIW-DSP is described. A technique to detect optimal processor architecture and instruction-level-parallelism for program execution is presented. Results of code generation experiments are presented for DSPstone benchmarks.