Dynamic measurement of critical-path timing

被引：24

作者：

Drake, Alan J. ^{[1
]}

Senger, Robert M. ^{[2
]}

Singh, Harmander ^{[3
]}

Carpenter, Gary D. ^{[1
]}

James, Norman K. ^{[4
]}

机构：

[1] IBM Res Corp, Austin, TX USA

[2] IBM Res, Yorktown Hts, NY USA

[3] AMD, Austin, TX USA

[4] IBM Syst Grp, Austin, TX USA

来源：

2008 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS | 2008年

关键词：

DVFS; critical path monitor; calibration;

D O I：

10.1109/ICICDT.2008.4567288

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A high bandwidth critical path monitor (1 sample/cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive to 20mV/bit A/C and 10mV/bit DC voltage changes, and less than 10 degrees C/bit temperature changes.

引用

页码：249 / +

页数：2

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