An FPGA-Based Malicious DNS Packet Detection Tool

被引:0
|
作者
Thomas, Brennon [1 ]
Mullins, Barry [1 ]
机构
[1] USAF, Inst Technol, Wright Patterson AFB, OH 45433 USA
来源
PROCEEDINGS OF THE 5TH INTERNATIONAL CONFERENCE ON INFORMATION WARFARE AND SECURITY | 2010年
关键词
DNS; FPGA; Virtex; exfiltration; botnet; tunnel;
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Billions and billions of packets traverse government and military networks every day. Often, these packets have legitimate destinations such as buying a book at amazon. com or downloading open source code using a File Transfer Protocol program. Unfortunately, the past few years have seen a massive increase in malicious, illegal, and suspicious traffic. One example is abusing the Domain Name System (DNS) protocol to exfiltrate sensitive data, establish backdoor tunnels, or control botnets. To counter this abuse and provide better incident detection, a physical hardware system is under development to detect these suspicious DNS packets. The system is constructed on a Xilinx Virtex-II Pro Field Programmable Gate Array (FPGA) and is based on a system originally developed to detect BitTorrent and Voice over Internet Protocol packets of interest. The first iteration prototype is limited in both processing speed (300 MHz) and by a 100 Mbps Ethernet interface. Despite the hardware shortfalls, preliminary experiments are promising for the system. The system inspects each packet, determines if it is a DNS packet, compares the first four characters of the lowest level domain against a DNS whitelist, and if the domain is not allowed, logs it for further analysis. The first experiment resulted in 100% malicious packet detection under an 88 Mbps network utilization. In the experiment, 50 malicious DNS packets were sent at one second intervals while the network was flooded with NetBIOS traffic. The second experiment resulted in an average of 91% malicious packet detection under an 88.7 Mbps network utilization. In the experiment, 2000 malicious DNS packets were sent as fast as possible while the network was flooded with non-malicious DNS traffic. For both experiments, DNS whitelist sizes of 1K, 10K, and 100K were used. Future work will focus on transferring the system to the Virtex-5 FPGA which contains a 550 MHz processor and a 1 Gbps Ethernet interface. In addition, the DNS whitelist size will be increased until the system fails to detect 50% of packets of interest. The goal is to determine if the system can be scaled to gigabit network speeds while also handling larger DNS whitelist sizes. The system seeks to aid network defenders in identifying and tracking malicious DNS packets traversing government networks while also providing better incident response awareness.
引用
收藏
页码:337 / 342
页数:6
相关论文
共 50 条
  • [31] FPGA-Based Optimization of Industrial Numerical Machine Tool Servo Drives
    Przybyl, Andrzej
    ELECTRONICS, 2023, 12 (17)
  • [32] MATLAB and FPGA-based interactive tool for exploring concepts on compressed sensing
    Rico-Aniles, Daniel
    Manuel Ramirez-Cortes, Juan
    Rangel-Magdaleno, Jose
    Gomez-Gil, Pilar
    Peregrina-Barreto, Hayde
    Alarcon-Aquino, Vicente
    COMPUTER APPLICATIONS IN ENGINEERING EDUCATION, 2015, 23 (06) : 921 - 930
  • [33] FPGA-based Real-time Abnormal Packet Detector for Critical Industrial Network
    Kang, Jiwoong
    Kim, Taein
    Park, Jaehyun
    2019 IEEE SYMPOSIUM ON COMPUTERS AND COMMUNICATIONS (ISCC), 2019, : 1199 - 1203
  • [34] FPGA-Based Network Microburst Analysis System with Flow Specification and Efficient Packet Capturing
    Yoshida, Shuhei
    Ukon, Yuta
    Ohteru, Shoko
    Uzawa, Hiroyuki
    Ikeda, Namiko
    Nitta, Koyo
    2020 IEEE 31ST INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 2020), 2020, : 29 - 32
  • [35] STRUCTURAL DECOMPOSITION AS A TOOL FOR THE OPTIMIZATION OF AN FPGA-BASED IMPLEMENTATION OF A MEALY FSM
    Barkalov, A. A.
    Titarenko, L. A.
    Barkalov, A. A., Jr.
    CYBERNETICS AND SYSTEMS ANALYSIS, 2012, 48 (02) : 313 - 322
  • [36] FAST FPGA-BASED ARCHITECTURE FOR PEDESTRIAN DETECTION BASED ON COVARIANCE MATRICES
    Martelli, Samuele
    Tosato, Diego
    Cristani, Marco
    Murino, Vittorio
    2011 18TH IEEE INTERNATIONAL CONFERENCE ON IMAGE PROCESSING (ICIP), 2011, : 389 - 392
  • [37] A FPGA-based intrusion detection system in IPv6
    Bin, He
    Fushan, Wei
    2007 INTERNATIONAL SYMPOSIUM ON COMPUTER SCIENCE & TECHNOLOGY, PROCEEDINGS, 2007, : 877 - 881
  • [38] FPGA-based intrusion detection system for 10 Gigabit Ethernet
    Katashita, Toshihiro
    Yamaguchi, Yoshinori
    Maeda, Atusi
    Toda, Kenji
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2007, E90D (12): : 1923 - 1931
  • [39] Development of a FPGA-Based Contactless Pulse Rate Detection System
    Lin, Yu-Chen
    Lin, Guan-You
    Lin, Yuan-Hsiang
    2016 2ND INTERNATIONAL CONFERENCE ON INTELLIGENT GREEN BUILDING AND SMART GRID (IGBSG), 2016, : 54 - 58
  • [40] FPGA-Based Neuro-Architecture Intrusion Detection System
    Hassan, A. A.
    Elnakib, A.
    Abo-Elsoud, M.
    ICCES: 2008 INTERNATIONAL CONFERENCE ON COMPUTER ENGINEERING & SYSTEMS, 2007, : 268 - 273