A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS

被引：28

作者：

Englund, Mikko ^{[1
]}

Ostman, Kim B. ^{[2
]}

Viitala, Olli ^{[1
]}

Kaltiokallio, Mikko ^{[3
]}

Stadius, Kari ^{[1
]}

Koli, Kimmo ^{[4
]}

Ryynanen, Jussi ^{[1
]}

机构：

[1] Aalto Univ, Dept Micro & Nanosci, Espoo 02150, Finland

[2] Nokia Technol Oy, Espoo 02610, Finland

[3] TDK Nord Oy, Espoo 02150, Finland

[4] Huawei Technol Oy, Helsinki 00180, Finland

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2015年 / 50卷 / 03期

关键词：

Blocker filtering; continuous-time; delta-sigma modulation; direct conversion receivers; direct delta-sigma receiver; frequency-translating; N-path filtering; noise shaping; RF sampling; wideband; FRONT-END; ADC;

D O I：

10.1109/JSSC.2015.2397193

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a wideband direct Delta Sigma receiver for the 0.7-2.7 GHz frequency range. The architecture embeds a wideband direct-conversion RF front-end into a continuous-time feedback Delta Sigma modulator, which initiates the analog-to-digital conversion of the selected channel already at the RF nodes. A feedback-type architecture enables simultaneous filtering of nearby interfering signals. The inductorless 40 nm CMOS receiver supports programmable Delta Sigma modulator coefficients and RF channel bandwidths up to 20 MHz. The receiver consumes 90 mW from a 1.1 V supply, and it provides a peak SNDR of 46 dB, NF of 5.9-8.8 dB, and an IIP3 of -2 dBm.

引用

页码：644 / 655

页数：12

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