Digital Dual Mixer Time Difference for Sub-Nanosecond Time Synchronization in Ethernet

被引：47

作者：

Moreira, Pedro ^{[1
]}

Alvarez, Pablo ^{[2
]}

Serrano, Javier ^{[2
]}

Darwezeh, Izzat ^{[1
]}

Wlostowski, Tomasz ^{[2
]}

机构：

[1] UCL, London, England

[2] CERN, Geneva, Switzerland

来源：

2010 IEEE INTERNATIONAL FREQUENCY CONTROL SYMPOSIUM (FCS) | 2010年

关键词：

D O I：

10.1109/FREQ.2010.5556289

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A digital architecture for the Dual Mixer Time Difference (DMTD) is presented. This architecture has several advantages over other phase frequency detectors such as being linear, not having a dead zone and with an accuracy within the sub-picoseconds range. The intrinsic phase noise present in all timing signals is the main cause of the limitation in the accuracy of this phase frequency detector. Therefore, this paper describes the advantages and disadvantages of the presented architecture as well as how its performance changes with the clock phase noise by showing some experimental measurements. The application of this architecture, for the use of Ethernet as both data and synchronization network, is also discussed.

引用

页码：449 / 453

页数：5