Low-Power HW Accelerator for AI Edge-Computing in Human Activity Recognition Systems

被引：0

作者：

De Vita, Antonio ^{[3
]}

Pau, Danilo ^{[1
]}

Parrella, Claudio ^{[2
]}

Di Benedetto, Luigi ^{[3
]}

Rubino, Alfedo ^{[3
]}

Licciardo, Gian Domenico ^{[3
]}

机构：

[1] STMicroelectronics, Syst Res & Applicat, Agrate Brianza, MI, Italy

[2] STMicroelectronics, Microcontrollers & Digital IC, Arzano, NA, Italy

[3] Univ Salerno, Dept Ind Engn, Fisciano, SA, Italy

来源：

2020 2ND IEEE INTERNATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE CIRCUITS AND SYSTEMS (AICAS 2020) | 2020年

关键词：

artificial intelligence; edge computing; hardware; low-power; human activity recognition; LESS STREAM PROCESSOR;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In this paper, an energy efficient HW accelerator for AI edge-computing in Human Activity Recognition is proposed. The system processes samples from a tri-axial accelerometer and classifies the human activities by using a novel Hybrid Neural Network (HNN) topology, which has been designed to reduce the computational complexity of the system while preserving its accuracy. The HW design improves the characteristics of the HNN by means of an architecture that is aimed to reduce the allocated physical resources and the memory accesses. While accuracy measured on ad-hoc dataset is 97.5 %, measurements from synthesis with CMOS 65 nm standard cells report power consumption of 6.3 mu W when the sensor output data rate is 25 Hz, normally used for HAR.

引用

页码：291 / 295

页数：5

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