Multigigahertz TSPC circuits in deep submicron CMOS

被引：0
|
作者：
Yuan, J
Svensson, C
机构：
[1] Univ Lund, Dept Appl Elect, S-22100 Lund, Sweden
[2] Linkoping Univ, Dept Phys & Measurement Technol, S-58183 Linkoping, Sweden
来源：
PHYSICA SCRIPTA | 1999年 / T79卷
关键词：
D O I：
10.1238/Physica.Topical.079a00283
中图分类号：
O4 [物理学];
学科分类号：
0702 ;
摘要：
Three circuits, two dividers and one accumulator, using the true single phase clocking (TSPC) technique were constructed in a partially scaled 0.1 mu M CMOS process. In the paper, the device model and the circuit design am described, and simulation and measurement results are given. Multigigahertz working frequencies are demonstrated at a circuit level by the combination of advanced CMOS technology and circuit technique.
引用
收藏
页码：283 / 286
页数：4
相关论文
共 50 条
  • [1] Analog circuits in ultra-deep-submicron CMOS
    Annema, AJ
    Nauta, B
    van Langevelde, R
    Tuinhout, H
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (01) : 132 - 143
  • [2] Leakage current in deep-submicron CMOS circuits
    Roy, K
    Mukhopadhyay, S
    Mahmoodi-Meimand, H
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2002, 11 (06) : 575 - 600
  • [3] A methodology for the characterization of arithmetic circuits on CMOS deep submicron technologies
    Estrada, A
    Jiménez, CJ
    Valencia, M
    VLSI Circuits and Systems II, Pts 1 and 2, 2005, 5837 : 902 - 912
  • [4] The impact of scaling down to deep submicron on CMOS RF circuits
    Huang, QT
    Piazza, F
    Orsatti, P
    Ohguro, T
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (07) : 1023 - 1036
  • [5] A study on split-output TSPC CMOS circuits
    Antaki, B
    Patenaude, S
    Trognon, L
    Savaria, Y
    ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE, 1997, : 1892 - 1895
  • [6] Power dissipation analysis and optimization of deep submicron CMOS digital circuits
    Gu, RX
    Elmasry, MI
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (05) : 707 - 713
  • [7] Optical Failure Analysis Technique in Deep Submicron CMOS Integrated Circuits
    Kim, Sunkwon
    Lee, Hyongmin
    Lee, Hyunjoong
    Woo, Jong-Kwan
    Cheon, Junho
    Kim, Hwan-Yong
    Park, Young June
    Kim, Suhwan
    JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2011, 11 (04) : 302 - 308
  • [8] Advanced failure detection techniques in deep submicron CMOS integrated circuits
    Rubio, A
    Altet, J
    Mateo, D
    MICROELECTRONICS RELIABILITY, 1999, 39 (6-7) : 909 - 918
  • [9] Simplified current and delay models for deep submicron CMOS digital circuits
    Mansour, MM
    Shanbhag, NR
    2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V, PROCEEDINGS, 2002, : 109 - 112
  • [10] Adaptive Thermal Monitoring of Deep-Submicron CMOS VLSI Circuits
    Zjajo, Amir
    van der Meijs, Nick
    van Leuken, Rene
    JOURNAL OF LOW POWER ELECTRONICS, 2013, 9 (04) : 403 - 413
12345