A Low Voltage Capacitor Based Current Controlled Sense Amplifier for Input Offset Compensation

With CMOS technology scaling, there is a significant increase in transistor threshold voltage mismatch and variations, which result in offset voltage in SRAM designs. A large offset voltage will enlarge SRAM bitline swing and negatively affect dynamic power consumption during a read operation, sensing decision correct rate and operation speed. This paper presents a low voltage capacitor based current controlled sense amplifier design for input offset compensation. The simulation results carried out in 90nm CMOS technology prove that the proposed offset compensation scheme can reduce the standard deviation of offset voltage by 4x compared to the conventional sense amplifier design with about 0.4%, 2.9% overheads in area and power respectively at 0.5V.