A 100MS/s 12-bit Coarse-Fine SAR ADC with Shared Split-CDAC

被引：1

作者：

Li, Manxin ^{[1
]}

Chen, Yongzhen ^{[1
]}

Ye, Fan ^{[1
]}

Ren, Junyan ^{[1
]}

机构：

[1] Fudan Univ, Dept Microelect, State Key Lab ASIC & Syst, Shanghai 201203, Peoples R China

来源：

2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2018年

基金：

中国国家自然科学基金;

关键词：

Coarse-Fine SAR ADC; Split-CDAC Array; DAC sharing; small area; low power; high speed;

D O I：

10.1109/ISCAS.2018.8351387

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 100MS/s 12-bit SAR ADC designed for terahertz imaging sensor is presented. The proposed ADC utilizes coarse-fine SAR architecture to relax reference requirement and improve operation rate. Split-CDAC structure is applied to reduce chip area, and its LSBs capacitors are reused as a coarse DAC. Redundant capacitor arrays are applied in both coarse and fine ADCs. A power-and-area-efficient ADC with high sampling rate can be realized with these techniques combined. The prototype is implemented in TSMC 1P9M 65nm-CMOS process. The simulation result with noise and other on board non-ideal effects shows that the ADC consumes 1.8 mW with an SNDR 65.7 dB and an SFDR of 77.0 dB with a Nyquist input at 1.2V power supply, achieving an ENOB of 10.6-bit and a FoM of 11.6 fJ/conv-step.

引用

页数：4

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