Cryogenic Comparator Characterization and Modeling for a Cryo-CMOS 7b 1-GSa/s SAR ADC

This paper reports the experimental characterization and modelling of a stand-alone StrongARM comparator at both room temperature (RT) and cryogenic temperature (4.2 K). The observed 6-dB improvement in the comparator input noise at 4.2 K is attributed to the reduction of the thermal noise and to the suppressed shot noise in the MOS transistors becoming dominant at cryogenic temperature. The proposed model is employed in the design of a loop-unrolled 2 x time-interleaved 1-GSa/s 7b SAR ADC for spin-qubit readout. As predicted by the comparator model, the ADC is noise-limited at RT to a SNDR of 38.2 dB at Nyquist input, while this improves to 41.1 dB at 4.2 K, now limited by distortion, thus resulting in the state-of-the-art FoMw for cryo-CMOS ADC of 20.9 fJ/conv-step.