A sub-600-mV, fluctuation tolerant 65-nm CMOS SRAM array with dynamic cell biasing

Fluctuation limitations on scaling CMOS SRAM cell transistor dimensions and operating voltages are demonstrated by measuring local stochastic distributions of 65-nm PDSOI CMOS SRAM cell storage node voltages during Read, Write, and Retention modes of operation. These measurements reveal insights into terminal voltage dependencies of cell margin distributions-observations that are engaged to increase cell immunity to random V-T fluctuations by several orders of magnitude by biasing the cell terminal voltages dynamically with a Read-Write asymmetry. Combinations of circuit techniques implementing these dynamic cell biasing schemes are demonstrated in a 9kb x 74b PDSOI CMOS SRAM array with a conventional 65 nm SRAM cell and an ABIST. Measurements demonstrate these techniques to enable V-MIN reductions of over 200 mV-lowering measured V-MIN to 0.54 V and 0.38 V/0.50 V for single and dual V-DD implementations, respectively. The techniques consume a 10%-12% overhead in area, impact performance marginally (<5%) and also enable over 50% reduction in cell leakage.