Ultra-low on-resistance high voltage (> 600 V) SOI MOSFET with a reduced cell pitch

A low specific on-resistance (R-S,R-on) silicon-on-insulator (SOI) trench MOSFET (metal-oxide-semiconductor-field-effect-transistor) with a reduced cell pitch is proposed. The lateral MOSFET features multiple trenches: two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX) (SOI MT MOSFET). Firstly, the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si; secondly, the oxide trenches cause multiple-directional depletion, which improves the electric field distribution and enhances the reduced surface field (RESURF) effect in the SOI layer. Both of them result in a high breakdown voltage (BV). Thirdly, the oxide trenches cause the drift region to be folded in the vertical direction, leading to a shortened cell pitch and a reduced R-S,R-on. Fourthly, the trench gate extended to the BOX further reduces R-S,R-on, owing to the electron accumulation layer. The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal-oxide semiconductor (LDMOS) to 632 V at the same half cell pitch of 21.5 mu m, and R-S,R-on decreases from 419 m Omega.cm(2) to 36.6 m Omega.cm(2). The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.