High-Performance 64-Bit Binary Comparator

被引：0

作者：

Anjuli ^{[1
]}

Anand, Satyajit ^{[1
]}

机构：

[1] Deemed Univ, FET MITS, E&CE Dept, Sikar, Rajasthan, India

来源：

PROCEEDINGS OF THE 2014 INTERNATIONAL CONFERENCE ON RELIABILTY, OPTIMIZATION, & INFORMATION TECHNOLOGY (ICROIT 2014) | 2014年

关键词：

Binary comparator; digital arithmetic; high-speed; low-; power; DIFFUSION-INPUT GDI; CMOS;

D O I：

暂无

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

High-performance 64-bit binary comparator is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This briefly presents comparison of modified and existing 64-bit binary comparator designs concentrating on power consumption and delay. Means some modifications have been done in existing 64-bit binary comparator design to improve the performance of the circuit. Comparison between modified and existing 64-bit binary comparator designs is calculated by simulation that is performed at 90nm technology in Tanner EDA Tool.

引用

页码：512 / 519

页数：8

共 12 条

[1]

Bellaouar A., 1995, LOW POWER DIGITAL VL

[2]

Chuang Pierce, 2012, IEEE T CIRCUITS SY 2, V59

[3] A New Low-Power High-Speed Single-Clock-Cycle Binary Comparator [J].

Frustaci, Fabio ;

Perri, Stefania ;

Lanuzza, Marco ;

Corsonello, Pasquale .

2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, :317-320

[4] High-performance and power-efficient CMOS comparators [J].

Huang, CH ;

Wang, JS .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (02) :254-262

[5] A mux-based high-performance single-cycle CMOS comparator [J].

Lam, Hing-Mo ;

Tsui, Chi-Ying .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2007, 54 (07) :591-595

[6] High-performance single clock cycle CMOS comparator [J].

Lam, HM ;

Tsui, CY .

ELECTRONICS LETTERS, 2006, 42 (02) :75-77

[7]

Leblebici Y., 2003, CMOS DIGITAL INTEGRA

[8]

Mano M.M., 2002, DIGITAL DESIGN, V3rd

[9] Asynchronous gate-diffusion-input (GDI) circuits [J].

Morgenshtein, A ;

Moreinis, M ;

Ginosar, R .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2004, 12 (08) :847-856

[10] Gate-diffusion input (GDI): A power-efficient method for digital combinatorial circuits [J].

Morgenshtein, A ;

Fish, A ;

Wagner, IA .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2002, 10 (05) :566-581

← 1 2 →