Small Area High Speed Configurable FFT Processor

被引：2

作者：

Zhang, Xiaoyu ^{[1
]}

Chen, Xin ^{[1
]}

Zhang, Ying ^{[1
]}

机构：

[1] Nanjing Univ Aeronaut & Astronaut, Coll Elect & Informat Engn, Nanjing, Jiangsu, Peoples R China

来源：

17TH IEEE INTERNATIONAL CONFERENCE ON IC DESIGN AND TECHNOLOGY (ICICDT 2019) | 2019年

基金：

中国国家自然科学基金;

关键词：

Fast Fourier Transformation; Radix-2(3) algorithm; Configurable structure;

D O I：

10.1109/icicdt.2019.8790913

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a design of a configurable FFT processor. The processor can support up to 4096-point FFT, using radix-2(3) algorithm which is optimized. The FFT processor can be configured as two structures which are pipeline structure and iterative structure. Pipeline structure is adopted at 512-point FFT operation and below. If FFT points are more than 512, iterative structure will be activated. The method of accessing the memory is also optimized. Because using multiple butterfly unit to process the data in parallel, the throughput can be improved. Finally, the function simulation and verification is made based on FPGA. The result shows that the processor performs well while utilizing less hardware resource.

引用

页数：4

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